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Performance and Reliability of Plastic-Encapsulated CMOS ASICs

Objective

The PLASIC project was concerned with the performance and reliability of plastic-encapsulated CMOS ASICs, and its goal was to develop guidelines on how to build and evaluate reliable plastic packages for VLSI devices for high reliability applications, such as those encountered in telecommunications, industrial control, and automotive and computer electronics.
This paper highlights the approach used for the development and evaluation of a low stress high pincount PQFP package for high reliability complementary metal oxide semiconductor application specific integrated circuit applications in the field of telecommunications, industrial control, automotive and computer electronics. Reliable die attach materials and moulding compounds for a low stress PQFP package are selected as a result of intensive material evaluation and process optimization, Mechanical stress simulations have been carried out to explain and confirm the mechanical stress measurements performed with the use of specially designed stress sensitive test devices. Reliability tests based on accelerated testing techniques have been performed using dedicated reliability test devices in order to assess the reliablity performance of the developed PQFP package. The developed package successfully passes highly accelerated stress and temperature cycling tests. The analysis with acoustic scanning microscopy shows that die package separation or delamination mainly occurs at the die corner on a limited number of devices.

The PLASIC project is concerned with the performance and reliability of plastic encapsulated complementary metal oxide semiconductor (CMOS) application specific integrated circuits (ASIC) and its goal is to develop guidelines on how to build and evaluate reliable plastic packages for very large scale integration (VLSI) devices for high reliability applications.

Packaging materials and processes are being studied and optimized, and the stress quantified. The selection of a low stress die attach material and molding compound has been performed and work on the assembly process has been completed.

Device shifts are being investigated and interdependencies between reliability and front end processing analysed, as well as between reliability and design rules.

Modelling tools are being developed with the aim of evaluating the thermal and mechanical stress induced on the ASIC devices by both the plastic packaging technology and the surface mounting of the packages on the system boards of end users.

2-dimensional plain strain finite element models of PQFP have been developed. Extensive work was carried out on these models to study the influence of complete and partial delamination on the thermomechanical stress distribution within the package.

3-dimensional finite element techniques with temperature dependent material properties have been used to investigate the packaging stress on the surface of a die encapsulated in a plastic material.

An innovative accelerated humidity test method (HAST) has been evaluated and compared to the conventional one (THB). As a result of this study, a method for fast qualification procedures, based on HAST and temperature cycling, has been issued to replace the existing ones, saving qualification time.
Special emphasis was put on the performance and reliability evaluation of complex and advanced plastic-packaged CMOS ASICs, processed using 1.0 micron technologies.

Coordinator

MIETEC
Address
Westerring, 15
9700 Oudenaarde
Belgium

Participants (5)

Alcatel SEL AG
Germany
Address
Lorenzstraße 10
70435 Stuttgart
ELEKTRONIKCENTRALEN
Denmark
Address
Venlighedsvej, 4
2970 Hoersholm
NATIONAL MICROELECTRONICS RESEARCH CENTRE
Ireland
Address
Prospect Row
Cork
SGS Thomson Microelectronics SA
France
Address
17 Avenue Des Martyrs
38340 Grenoble
Thomson Microelectronics Srl (SGS)
Italy
Address
Via Carlo Olivetti
20041 Agrate Brianza Milano