Periodic Reporting for period 1 - MINIMA EDA (Scaling Minima ultra-low energy computing technology to make intelligent wireless devices energy efficient)
Reporting period: 2022-01-01 to 2022-12-31
The number of wireless devices that rely on computing capability is growing rapidly. This has made integrated circuits the second biggest commodity in the world. Each of these devices has a special integrated circuit called a microprocessor. It is the component that provides computing capability.
Today there are 30 billion wireless devices like our smartphones that rely on integrated circuits. Leading experts believe that by 2035, there will be 1 trillion of these devices that rely on integrated circuits in
circulation. Continuing on this path, by 2035 these devices will consume 13 times the electricity consumed in Europe today. To mitigate this energy consumption and play our role in making the world more sustainable we have two options.
We either become less connected to the internet and use fewer devices. Or we make wireless devices more energy efficient. With Minima, we can make wireless devices more energy efficient.
We sell IP blocks that make microprocessors consume radically less energy to ensure that wireless intelligent devices are energy efficient. Our patented technology consists of hardware & software components that are directly integrated into microprocessors prior to manufacturing. This enhances performance & energy efficiency of wireless devices that power the Internet of Everything, that are often tasked with collecting & analysing data directly at the source. Our ultra-low energy computing technology allows wireless devices to work at their Minimum Energy Point (MEP) at any given computing load at any given time. Thus, it allows
wireless devices to adapt to changing circumstances like performance needs & process variations.
With Minima ultra-low power computing technology, we can reduce the microprocessor energy demand by up to 20x. This project allows us to productize our technology & move from a service to a product-lead business, ensuring that our technology can be integrated into consumer products in days not months.
Today there are 30 billion wireless devices like our smartphones that rely on integrated circuits. Leading experts believe that by 2035, there will be 1 trillion of these devices that rely on integrated circuits in
circulation. Continuing on this path, by 2035 these devices will consume 13 times the electricity consumed in Europe today. To mitigate this energy consumption and play our role in making the world more sustainable we have two options.
We either become less connected to the internet and use fewer devices. Or we make wireless devices more energy efficient. With Minima, we can make wireless devices more energy efficient.
We sell IP blocks that make microprocessors consume radically less energy to ensure that wireless intelligent devices are energy efficient. Our patented technology consists of hardware & software components that are directly integrated into microprocessors prior to manufacturing. This enhances performance & energy efficiency of wireless devices that power the Internet of Everything, that are often tasked with collecting & analysing data directly at the source. Our ultra-low energy computing technology allows wireless devices to work at their Minimum Energy Point (MEP) at any given computing load at any given time. Thus, it allows
wireless devices to adapt to changing circumstances like performance needs & process variations.
With Minima ultra-low power computing technology, we can reduce the microprocessor energy demand by up to 20x. This project allows us to productize our technology & move from a service to a product-lead business, ensuring that our technology can be integrated into consumer products in days not months.
Feature name: Minima Memory & DSP IP
- Feature description
Expanding Minima's core technology to other parts of the SoC beyond strictly the microprocessor. To enable this, we will develop Minima IP to be integrated into SoC memory & Digital Signal Processor (DSP) parts of the SoC.
- Needed technology/knowledge
Needed knowledge: Integrated circuit design, processor architecture, embedded software, DSP architecture, ultra-wide voltage & frequency scaling (UV-DVFS), dynamic margining for power, timing event processing
method.
Needed technology: Dynamic margining for power, UW-DVFS, dynamically Adaptable Algorithms, 6 / 96Minimum-energy point Integrated Circuits for Signal processing, timing event processing method, RISC-V, software API, sub-threshold voltage, near threshold voltage
- Technology/knowledge to be developed
Expanding Minima's core technology to other parts of the SoC beyond strictly the microprocessor. To enable this, we will develop Minima IP to be integrated into SoC memory & Digital Signal Processor (DSP) parts of the SoC.
For Memory IP: We will be adding parts of the IO periphery to enable variable timing. with the goal to only modify a minimum number of components to achieve the energy-reduction & constraint-removal goals. In short, we will be adding Minima IP to the Memory portion of the SoC.
For DSP Development: The Minima IP integrated DSP will be developed to the 20x energy improvement in extremely large designs where the number of low-level component (“gates”) is in multi-millions (for example a 4K video processor). In addition, the DSP requires software level enhancements especially in the compiler. So we will also develop the compiler & analysis software to offer the customer an interlinked product that eases their implementation effort.
Feature name Minima EDA Software
- Feature description
The minimum energy point (MEP) is different for each processor & application while it also changes during run-time. To maximise operation at the MEP, our solution determines the exact position of the point during run-time. This makes it vital for our IP to be modified slightly for all of the different applications.
Our feature is an IP-based model that adds both hardware (affecting power management, memory & processor) & software (affecting the API, OS & Middleware) components to the CPU & DSP processors to enable dynamic margining for power. To further maximise energy efficiency & savings we combine our dynamic margining with ultra-wide Dynamic Voltage and Frequency Scaling (UW-DVFS) in our middleware.
- Needed technology/knowledge
Needed technology/knowledge varies a bit for each specific application in our 5 pilot markets (IoT, AR/VR, Audio, Security & MCUs) but broadly speaking the technologies & knowledge we need are the following:
Needed knowledge: Integrated circuit design, processor architecture, embedded software, DSP architecture, ultra-wide voltage & frequency scaling (UV-DVFS), dynamic margining for power, timing event processing method, EDA software design.
Needed technology: Dynamic margining for power, UW-DVFS, dynamically Adaptable Algorithms, Minimum-energy point Integrated Circuits for Signal processing, timing event processing method, Risc V, Software API, sub-threshold voltage, near threshold voltage, EDA/CAD software (e.g. Cadence)
- Technology/knowledge to be developed
To scale our core technology across 5 market segments the Minima EDA software is vital. It reduces the custom integration work from 4 months to approximately 3 days. Leverging the EDA, customers are able to maximise operation at the MEP, by using our technology to determine the exact position of the point during run-time. As the point varies, it is vital for our IP to be modified slightly for all of the different applications. This is what EDA software achieves.
- Feature description
Expanding Minima's core technology to other parts of the SoC beyond strictly the microprocessor. To enable this, we will develop Minima IP to be integrated into SoC memory & Digital Signal Processor (DSP) parts of the SoC.
- Needed technology/knowledge
Needed knowledge: Integrated circuit design, processor architecture, embedded software, DSP architecture, ultra-wide voltage & frequency scaling (UV-DVFS), dynamic margining for power, timing event processing
method.
Needed technology: Dynamic margining for power, UW-DVFS, dynamically Adaptable Algorithms, 6 / 96Minimum-energy point Integrated Circuits for Signal processing, timing event processing method, RISC-V, software API, sub-threshold voltage, near threshold voltage
- Technology/knowledge to be developed
Expanding Minima's core technology to other parts of the SoC beyond strictly the microprocessor. To enable this, we will develop Minima IP to be integrated into SoC memory & Digital Signal Processor (DSP) parts of the SoC.
For Memory IP: We will be adding parts of the IO periphery to enable variable timing. with the goal to only modify a minimum number of components to achieve the energy-reduction & constraint-removal goals. In short, we will be adding Minima IP to the Memory portion of the SoC.
For DSP Development: The Minima IP integrated DSP will be developed to the 20x energy improvement in extremely large designs where the number of low-level component (“gates”) is in multi-millions (for example a 4K video processor). In addition, the DSP requires software level enhancements especially in the compiler. So we will also develop the compiler & analysis software to offer the customer an interlinked product that eases their implementation effort.
Feature name Minima EDA Software
- Feature description
The minimum energy point (MEP) is different for each processor & application while it also changes during run-time. To maximise operation at the MEP, our solution determines the exact position of the point during run-time. This makes it vital for our IP to be modified slightly for all of the different applications.
Our feature is an IP-based model that adds both hardware (affecting power management, memory & processor) & software (affecting the API, OS & Middleware) components to the CPU & DSP processors to enable dynamic margining for power. To further maximise energy efficiency & savings we combine our dynamic margining with ultra-wide Dynamic Voltage and Frequency Scaling (UW-DVFS) in our middleware.
- Needed technology/knowledge
Needed technology/knowledge varies a bit for each specific application in our 5 pilot markets (IoT, AR/VR, Audio, Security & MCUs) but broadly speaking the technologies & knowledge we need are the following:
Needed knowledge: Integrated circuit design, processor architecture, embedded software, DSP architecture, ultra-wide voltage & frequency scaling (UV-DVFS), dynamic margining for power, timing event processing method, EDA software design.
Needed technology: Dynamic margining for power, UW-DVFS, dynamically Adaptable Algorithms, Minimum-energy point Integrated Circuits for Signal processing, timing event processing method, Risc V, Software API, sub-threshold voltage, near threshold voltage, EDA/CAD software (e.g. Cadence)
- Technology/knowledge to be developed
To scale our core technology across 5 market segments the Minima EDA software is vital. It reduces the custom integration work from 4 months to approximately 3 days. Leverging the EDA, customers are able to maximise operation at the MEP, by using our technology to determine the exact position of the point during run-time. As the point varies, it is vital for our IP to be modified slightly for all of the different applications. This is what EDA software achieves.
Feature name Minima Memory & DSP IP
- Technology/knowledge to be developed
Expanding Minima's core technology to other parts of the SoC beyond strictly the microprocessor. To enable this, we will develop Minima IP to be integrated into SoC memory & Digital Signal Processor (DSP) parts of the SoC.
For Memory IP:
We will be adding parts of the IO periphery to enable variable timing. with the goal to only modify
a minimum number of components to achieve the energy-reduction & constraint-removal goals. In short, we will
be adding Minima IP to the Memory portion of the SoC.
For DSP Development:
The Minima IP integrated DSP will be developed to the 20x energy improvement in extremely large designs where the number of low-level component (“gates”) is in multi-millions (for example a 4K video processor). In addition, the DSP requires software level enhancements especially in the compiler. So we will also develop the compiler & analysis software to offer the customer an interlinked product that eases their implementation effort.
Feature name Minima EDA Software
- Technology/knowledge to be developed
To scale our core technology across 5 market segments the Minima EDA software is vital. It reduces the custom integration work from 4 months to approximately 3 days. Leverging the EDA, customers are able to maximise operation at the Minimum Energy Point (MEP), by using our technology to determine the exact position of the point during run-time. As the point varies, it is vital for our IP to be modified slightly for all of the different applications. This is what the EDA software achieves.
- Technology/knowledge to be developed
Expanding Minima's core technology to other parts of the SoC beyond strictly the microprocessor. To enable this, we will develop Minima IP to be integrated into SoC memory & Digital Signal Processor (DSP) parts of the SoC.
For Memory IP:
We will be adding parts of the IO periphery to enable variable timing. with the goal to only modify
a minimum number of components to achieve the energy-reduction & constraint-removal goals. In short, we will
be adding Minima IP to the Memory portion of the SoC.
For DSP Development:
The Minima IP integrated DSP will be developed to the 20x energy improvement in extremely large designs where the number of low-level component (“gates”) is in multi-millions (for example a 4K video processor). In addition, the DSP requires software level enhancements especially in the compiler. So we will also develop the compiler & analysis software to offer the customer an interlinked product that eases their implementation effort.
Feature name Minima EDA Software
- Technology/knowledge to be developed
To scale our core technology across 5 market segments the Minima EDA software is vital. It reduces the custom integration work from 4 months to approximately 3 days. Leverging the EDA, customers are able to maximise operation at the Minimum Energy Point (MEP), by using our technology to determine the exact position of the point during run-time. As the point varies, it is vital for our IP to be modified slightly for all of the different applications. This is what the EDA software achieves.