Feature name: Minima Memory & DSP IP
- Feature description
Expanding Minima's core technology to other parts of the SoC beyond strictly the microprocessor. To enable this, we will develop Minima IP to be integrated into SoC memory & Digital Signal Processor (DSP) parts of the SoC.
- Needed technology/knowledge
Needed knowledge: Integrated circuit design, processor architecture, embedded software, DSP architecture, ultra-wide voltage & frequency scaling (UV-DVFS), dynamic margining for power, timing event processing
method.
Needed technology: Dynamic margining for power, UW-DVFS, dynamically Adaptable Algorithms, 6 / 96Minimum-energy point Integrated Circuits for Signal processing, timing event processing method, RISC-V, software API, sub-threshold voltage, near threshold voltage
- Technology/knowledge to be developed
Expanding Minima's core technology to other parts of the SoC beyond strictly the microprocessor. To enable this, we will develop Minima IP to be integrated into SoC memory & Digital Signal Processor (DSP) parts of the SoC.
For Memory IP: We will be adding parts of the IO periphery to enable variable timing. with the goal to only modify a minimum number of components to achieve the energy-reduction & constraint-removal goals. In short, we will be adding Minima IP to the Memory portion of the SoC.
For DSP Development: The Minima IP integrated DSP will be developed to the 20x energy improvement in extremely large designs where the number of low-level component (“gates”) is in multi-millions (for example a 4K video processor). In addition, the DSP requires software level enhancements especially in the compiler. So we will also develop the compiler & analysis software to offer the customer an interlinked product that eases their implementation effort.
Feature name Minima EDA Software
- Feature description
The minimum energy point (MEP) is different for each processor & application while it also changes during run-time. To maximise operation at the MEP, our solution determines the exact position of the point during run-time. This makes it vital for our IP to be modified slightly for all of the different applications.
Our feature is an IP-based model that adds both hardware (affecting power management, memory & processor) & software (affecting the API, OS & Middleware) components to the CPU & DSP processors to enable dynamic margining for power. To further maximise energy efficiency & savings we combine our dynamic margining with ultra-wide Dynamic Voltage and Frequency Scaling (UW-DVFS) in our middleware.
- Needed technology/knowledge
Needed technology/knowledge varies a bit for each specific application in our 5 pilot markets (IoT, AR/VR, Audio, Security & MCUs) but broadly speaking the technologies & knowledge we need are the following:
Needed knowledge: Integrated circuit design, processor architecture, embedded software, DSP architecture, ultra-wide voltage & frequency scaling (UV-DVFS), dynamic margining for power, timing event processing method, EDA software design.
Needed technology: Dynamic margining for power, UW-DVFS, dynamically Adaptable Algorithms, Minimum-energy point Integrated Circuits for Signal processing, timing event processing method, Risc V, Software API, sub-threshold voltage, near threshold voltage, EDA/CAD software (e.g. Cadence)
- Technology/knowledge to be developed
To scale our core technology across 5 market segments the Minima EDA software is vital. It reduces the custom integration work from 4 months to approximately 3 days. Leverging the EDA, customers are able to maximise operation at the MEP, by using our technology to determine the exact position of the point during run-time. As the point varies, it is vital for our IP to be modified slightly for all of the different applications. This is what EDA software achieves.
