Objetivo
The objective of this 1 year project is to create a capability for the design and manufacture of two single-chip systems for two specific target market areas using deeply embedded application macrocells. These chips will perform far more complex functions than those today, and the complexity of their designs will require their designers to re-use and re-fine existing libraries of functional blocks. A functional block might be a video controller design, for example. The results will be one demonstrator chip in each of the two market areas designed using methodologies developed in the project.
The approach to the work :
ARM will provide core technology expertise to Hagenuk and ATML. ARM will receive input on architectural requirements and will work with Manchester University to investigate areas where Asynchronous techniques could bring a significant advantage. OptionExist will provide small user input to the project to ensure the design methodologies used can be applied by SMEs. Hagenuk have a specific interest in bit-map application macrocell algorithms on the ARM, and OptionExist are experts in this area.
The impact of the expected results :
ARM will gain knowledge of application macrocell design using its family of core processors and support cells. Hagenuk and ATML will generate application macrocells driven by current market need. Blocks in these cells will be re-usable, and targeted at specific application areas. Manchester will learn how to exploit Asynchronous techniques in a synchronous environment, and OptionExist will gain experience with advanced techniques and tools for integration, while providing an SME check-back to the project to ensure the new techniques are truly useful to SMEs. How the results will be exploited Hagenuk and ATML will use the work to improve their in-house design flow for targeted application designs. The project aims to test this flow by generating demonstrators which are immediately useful for further product development. ARM needs application-specific input to target its core more effectively, and to steer future ARM architecture decisions. Market specific algorithmic knowledge will improve ARM's ability to target ISDN and ATM macrocells, displacing existing and future competitor positions with a European embedded core design win.
Ámbito científico
Tema(s)
Convocatoria de propuestas
Data not availableRégimen de financiación
CSC - Cost-sharing contractsCoordinador
CB1 4JN Cambridge
Reino Unido