REQUEST is aimed at defining and applying an improved system design methodology by means of REusability and QUality ESTimation concepts.
Most of these serve the communications market, a domain in which Europe holds a leading position, but which is facing an increasing challenge from the rest of the world in terms of "Time-to-market" of new products. Their common motivation is to stimulate their product innovation with a focus on communications and industrial applications by means of improved competence in advanced design and testing. In particular they address system design from macrocell to board level. All of the partners share a long experience in VHDL language and related design methodologies.
As more and more automation of backend design is available, the added intellectual value moves from the cell level to the macro cell and higher levels. The specifications, models and descriptions of systems and subsystems have to be regarded as commercial capital which should be reused in an efficient way. Unfortunately, today the absolute value of these models is usually debatable. The keys for improvement in this domain are:
- greater reusability of modules at system level.
- increased level of abstraction for system design.
- enhanced quality of macrocells, chips and boards.
The consortium intends to achieve these objectives by defining, implementing a nd applying an advanced design methodology for quick and reliable system development. In order to guarantee early exploitation inside and outside the consortium, the methodology builds on any standard VHDL based design backend as available from commercial EDA vendors. The REQUEST partners have identified three kinds of new tools needed to implement the design methodology:
- Quality Tool-Set. The REQUEST project will develop quality metrics for high-level models with respect to complexity, testability, synthesizability and simulation efficiency. Tools will be implemented to analyze VHDL modules with respect to the metrics defined.
- Object-Oriented VHDL modelling tools. The main attention is on the development of an object-oriented extension of VHDL, called Objective VHDL, and a transformation preprocessor which translates Objective VHDL into standard VHDL to interface with commercial backends. Such kinds of tools have been shown to significantly improve coding efficiency, quality and reusability in software engineering.
- Extended synthesis capability. Extensions to the commercial behavioral synthesis tool SYNT will be developed in the project in order to meet the requirements of the new methodology. Both functional requirements, as well as language coverage requirements in order to handle descriptions at higher abstraction levels, will be considered.
In order to ensure the interoperability of these tools, all the developments will be organised around the commercial VHDL frontend and database, LVS, provided by LEDA. To facilitate the acceptance of the proposed methodology and its introduction into system houses, the REQUEST project will tackle the design efficiency problem by using five principles:
- the research is driven from a user's point of view, based on system companies requirements,
- the innovations are introduced in a pragmatic way based on concrete needs,
- tools will only be developed if not commercially available,
- the development will continuously be validated by the development of different applications using the design methodology and associated toolsets,
- the results are marketable outside the consortium through the CAD tool vendor partner (LEDA, SYNTHESIA).
Funding SchemeCSC - Cost-sharing contracts
91131 Issy-les- Moulineaux