Integrated testing environment for electronic designs
Customers' needs constantly change and what makes today's innovation may quickly become yesterday's technology. In order to keep abreast of technological trends to anticipate changes, design activities need to become more flexible, effective and time saving procedures. While extensive testing during design is useful for high performance, highly specialised and functional applications, it may often be redundant and difficult, resulting in significant delays. Meeting these needs, the proposed testability strategy involves a complete set of suitable methods and tools for use during the design phase. More specifically, designers may employ these highly efficient techniques when developing the Very high-speed integrated circuit Hardware Description Language (VHDL) code. This is a programming language for hardware modelling, with hardware ranging from complete systems (PCs) to the small logical gates on their internal integrated circuits. The combined techniques and tools satisfactorily address the design testability problems at three abstraction levels of the design process: the behavioural, the register transfer and the gate level. The analysis performed enables the designer not only to quickly detect hard-to-test code parts, but also to successfully predict possible later design failure. Moreover, the designer is also able to identify and remove redundant VHDL code, thus avoiding unnecessary complex interactions of system parts. This testability environment has been proved to be timesaving by avoiding design recycles and efficient without seriously affecting important design parameters, such as area and performance. The analysis of the VHDL description may be used reliably irrespective of the size of designs without any additional memory and time requirements. Offering various options for suitable architectures for facilitating testing, it may provide high testability and functional test quality of VHDL descriptions that not only supports, but also improves designing.