Cryptographic reduced instruction set processor smartcard

Informations projet

CRISP

N° de convention de subvention: 20847

Projet clôturé

Date de début 1 Novembre 1995

Date de fin 30 Avril 1998

Financé au titre de

• Specific research and technological development programme in the field of information technologies, 1994-1998

Coût total

€ 2 273 500,00

Contribution de l’UE

€ 1 350 000,00

Coordonné par

General Information Systems Ltd
United Kingdom

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Résultats exploitables

CRISP: smart card integrated circuit meets mass market needs

Public key cryptography (PKC) is an asymmetric cryptography system using two keys for encryption and decryption, one known only to the user and the other publicly available. This is widely accepted as one of the most secure encryption techniques available today. A powerful new cryptographic reduced instruction set processor (CRISP) has been developed which includes a unique security kernel. This guarantees the integrity and data independence of individual applications on a card, delivering a truly secure multisession environment. The project is developing a complete low cost smart card integrated circuit (IC) combining high speed and PKC security, with the high performance and silicon area efficiency of a reduced instruction set computing (RISC) architecture. The kernel itself can be configured to the target operating system at the time of issue and applications can be loaded remotely later, without compromising security. An instruction set optimized for smart cards includes comprehensive bit-manipulation instructions and a high level function library. The RISC processor delivers 20 million instructions per second (MIPS) so, for example, easily handles data encryption standard (DES) algorithms (typically 0.4 ms for a 64-bit block). It also provides the performance needed for processing of biometric data. A dedicated cryptographic logic unit (CLU) performs the fast, long integer calculations needed in PKC. The best known PKC algorithm is called RSA and the CLU can calculate an RSA signature with a 512-bit key in less than 50 ms. The core is optimized for reduced power consumption and runs at over 100 MHz, with an on-chip clock preventing penetration by external slow clocking.