An ASIC hard macro implementation of a DSP subsystem of a DECT mobile phone product featuring very low power consumption, dense layout (low cost) and adequate performance.
A prototype chip containing the developed ASIC hard macro and associated measurement results.
A high level architectural synthesis tool capable of power consumption optimisation and allowing the use of a wide variety of application specific execution units.
A library of DSP modules that can be used as application specific execution units in the above mentioned synthesis tool.
A library of standard cells for SGS-Thomson Microelectronics' 0.35 micron technology optimised for low power consumption.
A library of macros and layout generators for SGS-Thomson Microelectronics' 0.35 micron technology optimised for low power consumption.
Interfaces that are needed between the developed/existing tools/libraries to provide a seamless design path for ASICs.
The LP-DSP project aims at creating a capability to develop low power and low cost IC implementations of DSP applications. The capability will consist of an integrated design system, the necessary module/cell libraries and the target silicon process. The design system will be based on a state-of-the-art architectural synthesis tool that will be further developed in the project for power optimisation. The capability will be demonstrated by designing and implementing a subsystem for a mobile/cordless phone product.
Funding SchemeCSC - Cost-sharing contracts