- Development of back-end processing steps and modules for 0.25 micron CMOS by 4Q96.
- Implications of using low supply voltage (0.9 - 1.2 V) for 0.25 micron. CMOS will be assessed through the fabrication of specific test circuits. Measurement data will be available by 4Q96.
- Based upon the work of EP 9159 NOVA, concepts for 0.18 micron CMOS front-end modules will be investigated through the fabrication and testing of NMOST and PMOST devices. A lateral isolation module for 0.18 micron CMOS will be developed by 1Q97.
- Various techniques will be tested for the extension of 248 nm DUV lithography and the feasibility of 0.18 micron CMOS front-end patterning will be demonstrated.
- Insight into the key process parameters affecting device performance and reliability will be gained. Benchmarking with respect to competitive results obtained world-wide will be performed
The priorities of the European semiconductor industry will be supported through the assessment of key options for advanced CMOS process modules. The project is in phase with the most advanced world-wide efforts currently addressing 0.18 micron device architectures and defining 0.25 micron interconnect schemes. Target device specifications and lay-out rules for these technological modules will be defined in close interaction with industrial representatives. The results will be assessed and later exploited by the industrial partners in order to reduce their development costs (maximising the utilisation and minimising the risk). The 0.25 micron CMOS front-end process modules developed in EP 8002 ADEQUAT-2 will be modified for low-voltage applications.
Funding SchemeCSC - Cost-sharing contracts
2600 GB Delft
SN2 2QW Swindon
38054 Grenoble 9
5656 AA Eindhoven