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Content archived on 2024-05-14

Advanced developments for CMOS for 0.25 um and below

Exploitable results

The ADEQUAT+ project has achieved 0.18 micron front-end (processes in the first few layers) complementary metal oxide semiconductor (CMOS) processes, as well as 0.25 micron for the back-end (those in the final layers). Semiconductor fabrication is a complex multi-stage process and moving to 0.18 micron required addressing challenges at all stages, especially to find process sequences with more latitude. Alternative solutions for dielectrics, junctions and conductors were investigated, and new device architectures and novel schemes to connect them were developed. ADEQUAT+ showed the feasibility of CMOS transistors with 0.18 micron channel lengths. It demonstrated devices operating from supply voltages down to 1.8 V, and low-voltage technologies for 0.25 micron transistors. Layout rules for 0.25 micron back-end processing of 0.4 micron lengths were obtained, as well as 0.5 micron space for contacts and 0.4 micron interconnects, in the first metal layer. A stack of five metal layers using this process was also demonstrated.

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