Objetivo
It is the intention of the project not really to reach from a first shot these projected results which apply to "ideal" structures but to demonstrate the feasibility of both n-channel and p-channel vertical heterojunction field effect transistors proving far superior characteristics (drive current, off-state current, speed, transconductance...) made by a cost effective technology. In addition, a production friendly thin layer sequence will be allowed by a novel buffer layer concept. The validity of this concept will be demonstrated by the growth of a complete vertical stack as a demonstrator for CMOS feasibility.
In scaling down the classical planar MOS device towards deep submicron dimensions the most important technological limit encountered is the definition of the channel length by practical lithographic techniques. From a physical point of view the short channel effect which translates into Drain Induced Barrier Lowering (DIBL) and as such into threshold voltage roll off and off-state leakage current is the most important limitation.
In this project a new vertical heteroMOS structure is proposed which solves the above problem because of the following characteristics:
- the device is not a lateral but a vertical one: source/channel and drain regions are grown epitaxially. As such the device channel length is defined by the channel layer epitaxial growth and thus fully decoupled from lithographic limitations. Therefore much shorter channel lengths ( down to 20 nm) become feasible.
- at the source side of the device an heterojunction is used which keeps the barrier for conduction in the off-state constant and not affected by the drain voltage. In order to have conduction in the on-state the source side closest to the channel region is intrinsic. This allows for Fermi-level modulation by the action of the overlapping gate and thus conduction. The DIBL effect no longer exists.
In addition to solving the above limitations by the special architecture the heterojunction is made by a SiGe/ Si (pMOS) or SiGe/Ge (nMOS) combination. These materials are fortunately compatible with Si technology, allowing later for an easy integration into production.
Both pMOS and nMOS devices will be fabricated using 2 different approaches for the epitaxial growth, namely MBE and CVD.
The work in this project is organised into 5 workpackages:
- layer technology: active layers and buffer layers (needed for nMOS and later CMOS integration) with both solid source MBE and AP/RP CVD . Also the use of UHVCVD will be considered
- material characterisation and electrical transport properties study: physico-chemical analysis techniques and electrical and optical measurement techniques supporting the optimisation of active layers and buffers and quantising the parameters affecting carrier transport through the layers
- device manufacturing: vertical p-type and n-type test and demonstrator devices will be realised. This workpackage covers aspects like etching the vertical walls, depositing/growing the gate insulator, the gate electrode deposition.
- device characterisation (DC and AC including HF), device modelling and device simulation: results will lead to a deep physical understanding of the device operation, improved models and technology and predictions on circuit performances
- project management: WP 2 and 4 will provide us the guidelines for fine-tuning both technology and design in order to fully exploit the capabilities of the device and reach its optimised performance.
At the international workshop on 'Future Information Processing Technologies", (Porvoo, September 1995), attended by major Microelectronics companies and research sites, one of the conclusions was that the vertical MOS transistor is the device concept of the future. In establishing its potential advantages and assessing its performance with respect to today's classical scenarios, a technology which provides denser and faster structures, but uses the same generation of production equipment will be initiated.
Taking the present transfer activities of the SiGeHBT to production lines into consideration, the SiGe technology will be implemented in most of the Si lines, which will facilitate a seamless and low cost transfer of the new SiGe MOS into production.
Present projections based on for the operation of a 20 nm channel length vertical device at room temperature result in an on-current of 20000 µA/µm, an off-state current less than 1 pA/ µm2 , a transconductance of more than 3500 mS/mm, a VT of less than 0.3V at Vdd= 1V and an intrinsic carrier transit time of less than 1 ps. Given this outstanding performance compared to conventional CMOS one can foresee a realistic chance to win huge market segments in mainstream CMOS .
Ámbito científico (EuroSciVoc)
CORDIS clasifica los proyectos con EuroSciVoc, una taxonomía plurilingüe de ámbitos científicos, mediante un proceso semiautomático basado en técnicas de procesamiento del lenguaje natural. Véas: El vocabulario científico europeo..
CORDIS clasifica los proyectos con EuroSciVoc, una taxonomía plurilingüe de ámbitos científicos, mediante un proceso semiautomático basado en técnicas de procesamiento del lenguaje natural. Véas: El vocabulario científico europeo..
- ingeniería y tecnología ingeniería de materiales sólidos amorfos semiconductores amorfos
- ciencias naturales ciencias físicas electromagnetismo y electrónica microelectrónica
- ciencias naturales informática y ciencias de la información ciencia de datos tratamiento de datos
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Programa(s)
Programas de financiación plurianuales que definen las prioridades de la UE en materia de investigación e innovación.
Programas de financiación plurianuales que definen las prioridades de la UE en materia de investigación e innovación.
Tema(s)
Las convocatorias de propuestas se dividen en temas. Un tema define una materia o área específica para la que los solicitantes pueden presentar propuestas. La descripción de un tema comprende su alcance específico y la repercusión prevista del proyecto financiado.
Las convocatorias de propuestas se dividen en temas. Un tema define una materia o área específica para la que los solicitantes pueden presentar propuestas. La descripción de un tema comprende su alcance específico y la repercusión prevista del proyecto financiado.
Convocatoria de propuestas
Procedimiento para invitar a los solicitantes a presentar propuestas de proyectos con el objetivo de obtener financiación de la UE.
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Procedimiento para invitar a los solicitantes a presentar propuestas de proyectos con el objetivo de obtener financiación de la UE.
Régimen de financiación
Régimen de financiación (o «Tipo de acción») dentro de un programa con características comunes. Especifica: el alcance de lo que se financia; el porcentaje de reembolso; los criterios específicos de evaluación para optar a la financiación; y el uso de formas simplificadas de costes como los importes a tanto alzado.
Régimen de financiación (o «Tipo de acción») dentro de un programa con características comunes. Especifica: el alcance de lo que se financia; el porcentaje de reembolso; los criterios específicos de evaluación para optar a la financiación; y el uso de formas simplificadas de costes como los importes a tanto alzado.
Coordinador
3001 Leuven
Bélgica
Los costes totales en que ha incurrido esta organización para participar en el proyecto, incluidos los costes directos e indirectos. Este importe es un subconjunto del presupuesto total del proyecto.