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Content archived on 2024-05-07

Evaluation and demonstration of the simulation and enhancement tool

Objective

A very important part of the design flow is the design verification to improve the yield. The design and the layout have to be examined not only in the view of minimisation of silicon area used or high speed of the circuit, but also with respect to manufacturability. If we want to generate such robust designs, the existence of parameter variations resulting from unintentional variations in the process parameters must be accounted for.

A second issue of design verification is to find weaknesses in the layout. This is especially important for digital CMOS circuits as for a stable production line the yield is limited by functional yield losses (not parametric yield losses). Spot defects occurring unavoidably during the production process limit the achievable yield.

AISS Gmbh has developed YETI, a new yield estimation and optimisation tool which assimilates all experience and know-how from research to date. The basis of YETI is the computation of critical areas on the layout level especially for shorts between conducting regions. It enables the choice of different defect models, simulation of process induced layout deformations as observed in manufacturing like over/under etching, rounding of corners, optical proximity effect simulation and both numerical and visual output or results.

The evaluation and investigation of YETI by Siemens under industrial conditions for layout characterisation with respect to defect-related yield, compatible with the existing design flow, is the goal of this project. For selected circuits especially sensitive to failure modes caused by spot defects, the new tool will be applied to show how the yield can be calculated in advance and how the layout can be optimised for higher yield.

For the integration of electronic systems in telecommunications, automobiles and consumer electronics the demands with respect to the performance and time-to-market are increasing rapidly. Thus the efficient control of the concurrent engineering processes design, layout and production line performance is of essential importance for the optimisation of the overall function of integrated circuits.

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ACM - Preparatory, accompanying and support measures

Coordinator

Siemens Aktiengesellschaft
EU contribution
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Address
Balanstrasse 73
Muenchen
Germany

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Total cost

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