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Content archived on 2024-05-14

Single chip ISDN network terminator

Objective

Development of a single-chip Network Terminator for ISDN with minimum pincount and external components incorporating the following characteristics.
- fully ANSI and ETSI compliant U interface
- fully ITU compliant S interface
- two wire transmission NRZ 2B1Q 64 and 144 kbits/sec
- maintenance and service information signalling, possibility to
read out the state and coefficients
- automatic polarity adaptation, automatic gain control
- DSP with adaptive echo cancellation and decision feedback equalisation
- evaluation of the sampling instant by digital phase-locked-loop
- fast return to operation after line seizure due to data storage during
power down state, activation and deactivation including loop-control
- GCI interface for extended applications (NT plus mode)
Key macroblocks developed within the project will be accessible to third parties via the Alcatel-Mietec design library.

ISDN constitutes an important step in providing links which connect society to the information highway by expanding the bandwidth of the standard telephone gateway to a rate of four times higher than a sophisticated modem.
In this project Alcatel Mietec and Quante will join forces to develop circuit techniques and macroblocks which can be used to create a high performance single chip ISDN Network Terminator. The resulting chips will cut costs and power dissipation down to the level required for open market proliferation. This mixed-mode ASIC will contain advanced design techniques that combine complex digital circuit of up to 300,000 transistors including embedded data processors together with high performance analogue circuits delivering 12 bit accuracy at 15MHz sampling speeds.

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Topic(s)

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Funding Scheme

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CSC - Cost-sharing contracts

Coordinator

Alcatel Mietec
EU contribution
No data
Address
Westerring 15
9700 Oudenaarde
Belgium

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Total cost

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Participants (1)

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