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Conductive characteristics and mass fabrication of nanoscale integrated circuit nanowires

Objective

Objectives of the project are: Quantifying the limits and stability of electron conduction in short and long Nanowires, determining the low-temperature properties and the effects of space and charge quantisation on transport through Nanowires, quantifying, optimising and modelling transport properties of a molecular-metal junction and realising methods for parallel fabrication of Nanowires by elastomeric stamping.

This variety of phenomena and possibilities will be explored in wires ranging from 0.1µm to atomic dimensions and with length scales from 0.1µm to a few nanometres. Fabrication and characterisation using both high-resolution electron beam lithography and scanning probe techniques (STM, AFM, SNOM, SSFM, MFM, conducting AFM) will be used. Additionally first principle calculations and transport theory for the metallic and molecular nanowires will be performed so as to augment the experimental work. The members of the consortium have been chosen by their abilities and proven specialities to realise the points above.

Exploitation of the results of the project will open new perspectives in the coming era of nanoscale circuit integration. Terabytes of information storage will be possible where single molecules and the current flowing through them will be able to switch a specific unit in the circuit. However, even if the writing technique might be able to achieve a circuit interpretation, there is no way that this interpretation can take place and be functional if the conduction and the I-V characteristic of the interconnecting nanowires are not understood. The technological implications of these studies are the basis for the future integrated nanoscale device.

In the future development of nanoscale integrated circuits and devices a crucial element is the role of the interconnects. As the size of the active device elements approach the nanoscale, the corresponding wires that connect each element must similarly scale down.

Thus devices on the sub-100nm scale will require interconnects with sizes from 50nm down to molecular and atomic dimensions. We define such nanoscale interconnects as NANOWIRES. The challenge of this proposal consists in understanding the electron conduction and transport properties of these nanowires and to devise methods for parallel fabrication on the nanoscale.

In this project we are concerned with answering a number of crucial issues relating to the interconnect and junction. These issues will be relevant to the ultimate design of a nanoscale integrated circuit regardless of the nature of the active element. As such these issues represent a fundamental element of the road map leading towards nanoscale integration.

Funding Scheme

CSC - Cost-sharing contracts

Coordinator

THE CHANCELLOR, MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE
Address
Trinity Lane, The Old Schools,
CB2 1TN Cambridge
United Kingdom

Participants (5)

Centre National de la Recherche Scientifique
France
Address
Avenue Edouard Belin 16
31054 Toulouse
Chalmers University of Technology
Sweden
Address
Industrial Liaison And Dev. Office, Chalmers Scien
41288 Gothenburg
Ibm Research Division, Zurich Research Laboratory
Switzerland
Address
Saeumerstrasse 4
8803 Rueschlikon
Universidad Autonoma de Madrid
Spain
Address
Carretera De Colmenar Km 15
28049 Madrid
University of Copenhagen
Denmark
Address
Blegdamsvej 3
2200 Copenhagen