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Photonic integrated circuits for ultrahigh speed reconfigurable data networking

Final Activity Report Summary - TERABIT CHIPS (Photonic integrated circuits for ultrahigh speed reconfigurable data networking)

The Terabit Chips research program objectives targeted the design and realisation of advanced integrated optoelectronic circuits to augment state of the art electronics. This has become increasingly important with the broader public awareness and dissatisfaction with the increasing energy consumption in communications technologies. The circuits developed in this work have enabled pioneering and innovative monolithic subsystems for low-overhead, high efficiency data networks. Considerable operating energy savings have realised through intrinsically bandwidth-agnostic design in massive bandwidth circuits and loss-removal.

Multi-wavelength parallel processing has been an important aspect. The potential for routing high numbers of independent optical data channels simultaneously in the same circuit using the same components allowed direct energy savings and hardware reduction. The available bandwidth within the circuits was enhanced through the use of state of the art quantum dot technologies.

Interferometric techniques have been exploited through highly compact and integrated reconfigurable wavelength selective filters. The use of mode selective elements operating at the photonic level have been widely deployed in these optoelectronic circuits to facilitate highly compact and reproducible networking solutions.

Abstraction has played an important role in the design methodology. The end user, who is expected to be an electronic circuit designer requiring more bandwidth than his electronics will allow, is unwilling to engage at the photonic plane. Simplified electronic interfacing has therefore been devised in innovative crossbar building blocks. Here added complexity has been introduced to the photonic plane to facilitate ease of use at the system level. The overhead is a one-off design effort which has little impact on manufacture, while greatly simplifying deployment.

Integrated solutions have not only been shown to be compliant with multi-stage architectures, extensive work has also implemented multi-stage switching. By cascading integrated switch circuits in three stages, the architecture for a sixteen input, sixteen output circuit operating at 80Gb/s per path has been demonstrated experimentally enabling Terabit/second switching.

Off-the-shelf compliance is believed pre-requisite to the medium term acceptance of an otherwise highly disruptive approach to high capacity data routing. Therefore laboratory testing of data transmission has been performed with commercially available transceiver technologies. The incurred signal degradation has been repeatedly observed to be negligible for the more innovative epitaxial designs explored in the project.

Proof of principle circuit fabrication has been performed at regular intervals throughout the program with three process runs implemented directly within the project, and two process runs implemented through a multi-project wafer scheme pioneered at the host institution through the ePIXnet Network of Excellence.

Circuits have been made available for demonstrator studies through the BONE Network of Excellence. Two state of the art switching circuits using a quantum dot epitaxy were supplied to collaborating researchers at the University of Cambridge to verify the feasibility of switching networks in the access network. The feasibility for low penalty 10Gb/s routing between one and sixty four outputs has been explored using these circuits.

Scaling to high numbers of connections has been studied using sophisticated modelling techniques incorporating sophisticated combinations of rigorous travelling wave optoelectronic simulators, field resolved wavelength multiplexed payloads, and custom transceiver tools which enable the estimation of error rates and therefore electronic signal degradation. Up to sixty-four connections have been predicted for 100Gb/s payloads per connection. The route to multi-Terabit chips is therefore already being mapped out.

Assessment of circuits has been performed at a broad range of operating conditions. Payloads of 10Gb/s, 40 Gb/s and record 160Gb/s have been considered for serial transmission.