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SYSTEL (System design in Telecommunication using Supervise) has demonstrated the usefulness of using extensions to VHDL to improve the design process. An interface-based design using VHDL+ has been developed. This tool (SuperviseSV), made by ICL, enables models to be built more easily and rapidly, thus reducing time-to-market.
The extensions to VHDL (VHDL+) were used to model a telecommunication system. The product comprises the SuperviseSV Compiler, the SuperviseSV Methodology and the VHDL+ language.
VHDL+ is a superset of VHDL which extends the language capability up to the system design level.
Systems can be described in VHDL+ at a higher level of abstraction than is possible with conventional languages. The compiler provides syntax and semantic checks and the ability to generate an equivalent VHDL description, which can then be simulated on any VHDL simulator. System level design allows early capture of design descriptions before implementation details are decided. It also offers earlier simulation of high level design ideas and alternatives with minimal specification code. The project demonstrated that VHDL+ was of benefit in areas other than the design of high performance computer servers, i.e. telecommunications systems: Ericsson have been able to improve their design processes thus reducing time-to-market by up to 50%.
Project URL: +44-161-2305757
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