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A High-Performance CMOS/Bipolar Process for VLSI Circuits

Objective

The objective of the BICMOS project has been the development of a VLSI technology combining, on a single chip, high-density CMOS circuitry with bipolar circuitry of similar density, but better suited to specific tasks, such as high performance analogue circuits.
The objective of the bipolar complementary metal oxide semiconductor (BICMOS) project has been the development of a very large scale integration (VLSI) technology combining, on a single chip, high density complementary metal oxide semiconductor (CMOS) circuitry with bipolar circuitry of similar density, but better suited to specific tasks, such as analogue interfacing with the external world. The main effort has been on the technological side, in the development of methods which allow both bipolar and CMOS transistors to be made in compatible process steps, and in dimensions comparable to those obtained in CMOS-only technology. In parallel with the technological work, design methods for this specific type of circuit (mixing analogue and digital functions) have been under development, along with studies to determine for various types of application, the most appropriate division of subsystems between the 2 circuit technologies.
A BICMOS-2 (1.2 micron feature size in CMOS and 0.9 to 1.2 micron in the bipolar part) has been developed. A bipolar transit frequency of 10 GHz has been achieved. Isolated vertical pnp transistors have been incorporated for analogue applications. A number of circuits have been designed and processed.
They include: a 10-bit video analogue to digital (AD) converter with 13.5 MHz sampling rate and over 100 k complexity for a total chip size of 80 mm{-2}; a 2k emitter coupled logic (ECL) gate array with a 16k static random access memory (SRAM); a finite impulse response (FIR) filter for application in high definition television (HDTV) and 8-bit AD converter for a data rate of 75 MHz and including an antialiasing filter; a 200 kHz, 16 bit AD converter (30-50k complexity) with error correction and autocalibration.
The partners have further developed a BICMOS-3 technology aiming at a further improvement in performance of CMOS and bipolar devices, a reduction in process complexity and a CMOS packaging density that is competitive with 0.7-0.8 micro n CMOS technologies. In this process the following circuits have been designed and processed: the multiplication/division unit for a 270 MHz reduced instruction set computer (RISC) processor, an ECL current mode logic (CML) library consisting of 280 core and 25 input/output (IO) cells (Phoenix VLSI) based on a gate array resembling about 50k gates, a high speed serial link.
The main effort has been on the technological side, in the development of methods which allow both bipolar and CMOS transistors to be made in compatible process steps, and in dimensions comparable to those obtained in CMOS-only technology. In parallel with the technological work, design methods for this specific type of circuit (mixing analogue and digital functions) have been under development, along with studies to determine, for various types of application, the most appropriate division of sub-systems between the two circuit techniques.

Coordinator

NEDERLANDSE PHILIPS BEDRIJVEN BV
Address
Kastanjelaan, 1218
5600 MD Eindhoven
Netherlands

Participants (5)

ENTWICKLUNGSZENTRUM FUER MIKROELEKTRONIK
Austria
Address
Siemensstr. 2
9500 Villach
INSTITUTO DE ENGENHARIA DE SISTEMAS E COMPUTADORES
Portugal
Address
Apartado 10105, Rua Alves Redol, 9
1017 Lisboa
Phoenix VLSI Consultants Ltd
United Kingdom
Address
Water Lane
NN12 7RQ Towcester
Siemens AG
Germany
Address
Balanstraße 73
81541 München
UNIVERSITY OF DUBLIN
Ireland
Address
Trinity College
Dublin 2