Final Report Summary - MANON (Methods for Advanced Multi-Objective Optimization for eDFY of complex Nano-scale Circuits)
Cost control, production efficiency, cycle time and yield are critical quality benchmarks for nano-electronics productions. An increasingly important downside of nano-CMOS technology scaling is the fact that the figures of merit of a circuit, such as performance and power, have become more and more sensitive to uncontrollable statistical process variations (PV). To ensure stable manufacturability and secure high manufacturing yield, it is mandatory to take into account the inevitable statistical process variations already in the design phase. In this context, multi-objective optimization algorithms and statistical circuit modelling on device and behavioural levels are a viable solution to nano-electronics production quality.
The project MANON is the joint venture between academies, industry and SME. The goal of this joint venture is to create a Transfer of Knowledge between the organizations in order to pass the mathematical know how on multi-objective optimization, symbolic techniques and numerical statistical simulation on one side, the industrial design experience, real test cases availability and Electronic Design Automation (EDA) software modelling skills on the other. The scope of the research activity has been to create PV-aware and PV-robust circuit design techniques, tools and models in the frame of the analogue and mixed-signal circuit industrial design.
Academic and industrial state of the art optimization and methods to generate circuits’ behavioural models have been analysed on selected industrial test cases. The research activities started from the analysis of what was at the beginning of the project the state of art in the industrial design flow for the generation of electrical Design For Yield (e-DFY) models and from its limitations. Such an industrial flow, based on the Response Surface Methodology (RSM), did not allow anymore the generation of accurate e-DFY models on most recent circuits and PDKs. However, these results have paved the way for the implementation of more powerful solutions based on different methodologies:
1) A combination of machine learning methods (Neural Networks and Support Vector Machine) and a Derivative-free mixed-integer black-box optimization algorithm to be used for faster circuits yield estimation.
2) The usage of Symbolic Model Order Reduction (SMOR) techniques for reducing the complexity of the system of differential equations describing the behaviour of an integrated circuit, thus reducing drastically the simulation time
3) Enhance the RSM models accuracy using RBF (radial basis functions) with automatic width variation, per function and/or input parameter
The most promising methodologies in terms of accuracy and performance have been implemented in a software prototype that has been validated on selected industrial test cases. The obtained results have shown that:
1) The new methodologies are able to create models with a higher accuracy and consequently are able to manage a greater number of design variables (MOS widths and lengths etc. etc.), environment variables (bias Voltage, temperature, etc. etc.) and process variables (statistically described through Gaussian or uniform distribution)
2) The new methodologies are better performing in terms of time requirements because they allow the extraction of behavioural models with a reduced number training points. Less training points means less circuit simulations which translates in a considerably reduction of the usage of the hardware resources needed for model generation
3) The new optimization algorithms investigated during the project are able to reach an accuracy comparable with the reference methodologies based on the maximization of the worst case distances which, however, has shown always a higher accuracy for each test case taken into consideration
In addition, two more activities, not planned at the beginning of the project, have been carried out:
• A new methodology based on the combined usage of Artificial Neural Network and Bezier curves for the generation of statistical aware circuit models that can speed up time domain simulations has been investigated. The preliminary results have been very promising and have set the basis of future research and development activities.
• The MANON eDFY methodologies have been extended to the digital domain. A CMOS library has been built as additional test case. The target of this activity was to set up a circuit test case with strong non-linearity for optimization and modelling in the context of Design for Yield. The circuits have been characterized in 45 nm, 32 nm and 22 nm technology. Experiments on the optimization of digital standard cells (flip-flop) taken from the library have been conducted leading to partially successful results.
Overall, we can conclude that the success criteria defined at the beginning of the project have been reached, with a considerable improvement in terms of accuracy and computational effort mainly observed in the phase of surrogate models generation. An important outcome of the entire project is the software prototype, which has proved to be really useful and usable in ST’s industrial environment.
From the Transfer of Knowledge point of view, MANON has given the possibility to involve in the project two More Experienced Researchers (MER) for 24 months from outside the Consortium. ST has had the opportunity to send an Experienced Researcher (ER) for 18 months at ITWM premises, and 6 months at Sapienza University in Rome. The ST’s ER has acquired competences in the field of Support Vector Machines and Artificial Neural Networks, symbolic methods and optimization algorithms applied to the design of electronic circuits and has shared the ST IPs (Intellectual Properties) and design workflow.
An Early Stage Researcher (ESR) from ITWM has been trained for 24 months in ST inside the industrial environment. From UNIRM two ESRs have been seconded for 14 months to complement their PHD works with a training on the job inside a semiconductor industry (in the design centre) and in an EDA software house. The former has spent six months in ST and two months in MUNEDA. The latter has spent in MUNEDA 6 months.
The project MANON is the joint venture between academies, industry and SME. The goal of this joint venture is to create a Transfer of Knowledge between the organizations in order to pass the mathematical know how on multi-objective optimization, symbolic techniques and numerical statistical simulation on one side, the industrial design experience, real test cases availability and Electronic Design Automation (EDA) software modelling skills on the other. The scope of the research activity has been to create PV-aware and PV-robust circuit design techniques, tools and models in the frame of the analogue and mixed-signal circuit industrial design.
Academic and industrial state of the art optimization and methods to generate circuits’ behavioural models have been analysed on selected industrial test cases. The research activities started from the analysis of what was at the beginning of the project the state of art in the industrial design flow for the generation of electrical Design For Yield (e-DFY) models and from its limitations. Such an industrial flow, based on the Response Surface Methodology (RSM), did not allow anymore the generation of accurate e-DFY models on most recent circuits and PDKs. However, these results have paved the way for the implementation of more powerful solutions based on different methodologies:
1) A combination of machine learning methods (Neural Networks and Support Vector Machine) and a Derivative-free mixed-integer black-box optimization algorithm to be used for faster circuits yield estimation.
2) The usage of Symbolic Model Order Reduction (SMOR) techniques for reducing the complexity of the system of differential equations describing the behaviour of an integrated circuit, thus reducing drastically the simulation time
3) Enhance the RSM models accuracy using RBF (radial basis functions) with automatic width variation, per function and/or input parameter
The most promising methodologies in terms of accuracy and performance have been implemented in a software prototype that has been validated on selected industrial test cases. The obtained results have shown that:
1) The new methodologies are able to create models with a higher accuracy and consequently are able to manage a greater number of design variables (MOS widths and lengths etc. etc.), environment variables (bias Voltage, temperature, etc. etc.) and process variables (statistically described through Gaussian or uniform distribution)
2) The new methodologies are better performing in terms of time requirements because they allow the extraction of behavioural models with a reduced number training points. Less training points means less circuit simulations which translates in a considerably reduction of the usage of the hardware resources needed for model generation
3) The new optimization algorithms investigated during the project are able to reach an accuracy comparable with the reference methodologies based on the maximization of the worst case distances which, however, has shown always a higher accuracy for each test case taken into consideration
In addition, two more activities, not planned at the beginning of the project, have been carried out:
• A new methodology based on the combined usage of Artificial Neural Network and Bezier curves for the generation of statistical aware circuit models that can speed up time domain simulations has been investigated. The preliminary results have been very promising and have set the basis of future research and development activities.
• The MANON eDFY methodologies have been extended to the digital domain. A CMOS library has been built as additional test case. The target of this activity was to set up a circuit test case with strong non-linearity for optimization and modelling in the context of Design for Yield. The circuits have been characterized in 45 nm, 32 nm and 22 nm technology. Experiments on the optimization of digital standard cells (flip-flop) taken from the library have been conducted leading to partially successful results.
Overall, we can conclude that the success criteria defined at the beginning of the project have been reached, with a considerable improvement in terms of accuracy and computational effort mainly observed in the phase of surrogate models generation. An important outcome of the entire project is the software prototype, which has proved to be really useful and usable in ST’s industrial environment.
From the Transfer of Knowledge point of view, MANON has given the possibility to involve in the project two More Experienced Researchers (MER) for 24 months from outside the Consortium. ST has had the opportunity to send an Experienced Researcher (ER) for 18 months at ITWM premises, and 6 months at Sapienza University in Rome. The ST’s ER has acquired competences in the field of Support Vector Machines and Artificial Neural Networks, symbolic methods and optimization algorithms applied to the design of electronic circuits and has shared the ST IPs (Intellectual Properties) and design workflow.
An Early Stage Researcher (ESR) from ITWM has been trained for 24 months in ST inside the industrial environment. From UNIRM two ESRs have been seconded for 14 months to complement their PHD works with a training on the job inside a semiconductor industry (in the design centre) and in an EDA software house. The former has spent six months in ST and two months in MUNEDA. The latter has spent in MUNEDA 6 months.