Fault-free designs for nano-scale circuits
To ensure reliable manufacturability of complementary metal-oxide semiconductor circuitry, researchers proposed to link existing design methods with computer-assisted design. Statistical modelling to assess the impact of inevitable process variations and doping fluctuations promise significant improvements in nano-electronics quality and production efficiency. Within the EU-funded project MANON (Methods for advanced multi-objective optimization for eDFY of complex nano-scale circuits) the researchers explored optimisation algorithms, symbolic techniques and numerical simulations. Three different approaches including the use of symbolic model order reduction (SMOR) techniques and machine learning methods were investigated. Researchers analysed the current state of the art in electric design for yield and its limitations. Selected test cases revealed that the response surface methodology currently used in the industry did not produce accurate models. High order non-linearities and the enormous number of parameters to be considered make it difficult to characterise the performance behaviour properly. On the other hand, the usage of SMOR techniques reduces the complexity of the system of differential equations that describe the behaviour of an integrated circuit. A combination of support vector machines or artificial neural networks together with suitable optimisation algorithms reduce drastically the simulation time for the circuit yield estimation. The MANON project represents the success story of a long-lasting joint venture between academia and industry including small businesses. The aim was to develop mathematical know-how to create process variation-aware circuit design techniques and numerical statistical simulations. The outcome exceeded the initial goals. MANON's partially automated method to generate parameterised behavioural models should reduce the effort involved in model generation and ensure model simulation accuracy. Models developed should enable designers to perform system-level verification and fine-tune designs based on responses to operating conditions and process variations.
Keywords
Nanoelectronics, complementary metal-oxide semiconductor, computer-assisted design, SMOR, machine learning
