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Silicon sUbstrates from an inteGrated Automated pRocess

Final Report Summary - SUGAR (Silicon sUbstrates from an inteGrated Automated pRocess)

Executive Summary:
The Sugar project aims at reducing the thickness of the Si substrates used in nowadays photovoltaic cells. To be able to realize photovoltaic devices on thin Si substrates, two bottlenecks need to be overcome. First of all, there is no proven cost-effective method to manufacture Si substrates of 50 µm. Secondly, the experience in industry with handling and processing such thin and fragile devices is very limited. Consequently, the two main objectives of the project are to tackle these two bottlenecks. The first objective is the design of a processing sequence that takes as input thick Si wafers and gives as output large-area (30 cm2) ultra-thin wafers (~50 µm) by an industrial viable process. The second objective is the demonstration of a PV module process adapted to ultra-thin material fully based on carrier processing, including on definitive glass superstrate, with a module consisting of at least two cells and a conversion efficiency of 17% or more. The expected impact of the project is to further reduce costs of solar modules, by accelerating the move towards higher efficiency solar cells and the move towards thinner silicon wafers. At the start of the project, the partnership consisted of four academic and/or research institutes (imec, Fraunhofer IPA, Armines – Centre de Mise en Forme des Materiaux and FFCUL – University of Lisbon) and six companies (Bosch – Rexroth, Ferro, Dow Corning, AMAT – Baccini, Semilab and 4Pico). At the very beginning of the project Bosch – Rexroth decided to leave the consortium. At the same moment a new partner was asked to join the consortium: Ferro Hanau. This new partner was able to supply know-how related to the first objective.

To address the first objective, the Sugar consortium proposes an innovative method to manufacture 50-µm thick wafers without kerf loss. This method, called Slim-cut, relies on the application of a stress-inducing layer on top of the Si substrate. Upon a thermal treatment, the induced stress in the substrate leads to controlled crack propagation parallel to the surface at a given depth. At the start of the project, the consortium worked on a Slim-cut process based on a stress-inducing layer of two metal pastes. This process had some drawbacks. From the modelling work it was inferred, and later on experimentally verified, that materials other than the original Ag-Al paste system could be used as a stress-inducing layer. A dispensed epoxy was selected as an alternative. By this material, and assisted by simulations, thin Si foil could be obtained with a limited thermal budget (curing at 150 °C followed by cooling at room temperature). The resulting foils have an effective lifetime ~50 µs, a thickness of ~100 µm and an area up to 7x7 cm2. Multiple lift-off from the same substrate was demonstrated. Cost of one lift-of has been calculated to be 0.89 €/foil for a 156x156 mm2 foil.

The work related to the second objective focusses on cell processing at module level. This implies that the thin Si foils are permanently bonded to their module glass as early as possible in the process flow. Once bonded, the fragile foils are mechanically supported by the glass. The rest of the process flow is executed on the cells bonded to the glass. The required process steps for this flow are developed during the project. This includes a process to apply uniform thin silicone layers on glass, which allows bonding thin foils to the substrate. One of the other developed steps was the realization of an interdigitated pattern of a-Si:H emitter and a-Si:H BSF on the rear of the cells. This low temperature process is compatible with the bonding. This complete process is demonstrated in functional devices with efficiencies up to 17.9%. To be able to combine several cells on the same substrate into a module, also the required module steps were demonstrated: cell-to-cell interconnection, additional silicone and backsheet application. These techniques allowed not only fabricating single cells bonded to glass, but also mini-modules of several wafers or cells bonded to the same glass superstrate. Reliability tests on these mini-modules showed the reliability of the cell-to cell interconnection. Instability in damp heat of a-Si:H passivating layers on encapsulated wafers was identified. Approaches to solve this problem were investigated, and solutions were found. A concept for volume manufacturing, following this complete flow, has been studied. This included not only a conceptual study but also the development of several handling steps: application of laser notches to induce the crack propagation in the Slim-cut process, gripping of thin wafers and precise and fast placement of wafers on the silicone-covered glass.

Project Context and Objectives:
Industrial solar wafers are today in the range of 160 µm, a thickness that embodies the compromise between breakage rate (industrial yield) and silicon material cost. However, arguments remain to keep on reducing the thickness of the material used:
• The cost of the raw material (feedstock) is estimated to still account for 15% of the module cost.
• Literature shows that when limited by Auger recombination, the performance of solar cells peaks at a thickness of approximately 50 µm.
At this moment, there are two main drivers to keep the thickness relatively large at 160 µm. Both drivers are technological:
• There is nowadays no proven cost-effective method to manufacture solar substrates of 50 µm.
• There is nowadays no industrial method to process solar cells on 50-µm wafers.
The Sugar project proposes two innovative technologies which can be developed and used independently, the first one to produce solar wafers of 50 microns, and the second one to process them into solar cells.

a. First Sugar objective: wafering 50-µm thick wafers
The first bottleneck is tackled in Sugar by proposing an innovative method to manufacture 50-µm thick wafers without kerf loss. This method, called Slim-cut, relies on thermo-mechanical treatments: a high stress field is applied to a silicon wafer by a stress inducing layer. Upon a temperature treatment, a crack propagates in the silicon substrate parallel to the surface at a given depth. The top silicon layer is separated from the parent substrate and processed into a solar cell. The parent substrate can be re-used.
The first Sugar objective: Design of a processing sequence, consisting of tools and proven handling concepts, that takes as input Si tiles (wafers with a thickness > 1 cm) and gives as output large-area (30 cm2) ultra-thin wafers (~50 µm) by an industrial viable process. This sequence will be comprised of a number of process and handling steps that will be developed in the course of the project.

b. Second Sugar objective: thin-film-like high efficiency module level processing of bulk solar cell
The second bottleneck is related to the wafer-based approach that is nowadays dominating the standard c-Si technology. In the module concept developed within Sugar, the cell processing will be achieved on module level and not on wafer level.
The general description of the process resembles very much the standard thin-film process: deposition on several square meters of a-Si, metallization and patterning. The difference lies in the starting material. Instead of starting from TCO-covered glass, our approach starts from a set of ultra-thin Si wafers bonded to the glass. The thin crystalline Si wafers in combination with the amorphous-Si emitters guarantee high conversion efficiencies, while the module glass (superstrate) fully supports the fragile wafers during cell processing. Moreover, processing at module level provides an additional volume cost reduction potential.
In this flow, the ultra-thin Si material can be obtained by the Slim-cut method, but not necessarily.
The second Sugar objective: Demonstration of a PV module process adapted to ultra-thin material fully based on carrier processing (including on definitive glass superstrate), with a module consisting of at least two cells and a conversion efficiency of 17% or more (aperture area).

These two main objectives led to two lines in the strategy of the Sugar project, as depicted in Fig.1. This strategy has been translated in seven work packages:
• WP1: Project management
• WP2: Slim-cut development
• WP3: Gripping and handling
• WP4: Bonding and encapsulation
• WP5: Module level processing
• WP6: Characterization and reliability testing of modules
• WP7: Integration, demonstration, concept and cost modelling
Most of the work packages are arranged along one of the lines, but they come together in the final work package seven.
At the start of the project, the partnership consisted of four academic and/or research institutes (imec, Fraunhofer IPA, Armines – Centre de Mise en Forme des Materiaux and FFCUL – University of Lisbon) and six companies (Bosch – Rexroth, Ferro, Dow Corning, AMAT – Baccini, Semilab and 4Pico). At the very beginning of the project Bosch – Rexroth decided to leave the consortium. At the same moment a new partner was asked to join the consortium: Ferro Hanau.

Project Results:
WP2: Slim-cut development
The goal of this work package was to develop the Slim-cut process. At the start of the project, the consortium worked on a Slim-cut process based on a stress-inducing layer of two metal pastes. This process had some drawbacks. The process needed a high temperature step (650-900 °C) to induce lift-off. The metal pastes are rather expensive layers. Next to that, the electronic quality of the foil was low due to structural defects and possibly metal diffusion from the pastes during the high temperature step. Moreover, the metals proved to be difficult to remove from the foil after lift-off. From the modelling work it was inferred, and later on experimentally verified, that materials other than the original Ag-Al paste system could be used as a stress inducing layer. Consequently, glass pastes, Ni layers and polymers were compared on their deposition method, ability to lift-off a Si foil, quality of the foil after lift-off and easiness of cleaning the foil after lift-off.

A dispensed epoxy was chosen to be the most suited one based on these criteria. The process with the epoxy material has a much lower thermal budget (curing at 150 °C followed by cooling at room temperature). Effective lifetimes ~50 µs were reproducibly obtained at the sites of FFCUL and imec. By studying the crack propagation in the foil, foils with an area up to 7x7 cm2 could be realised. Also multiple lift-off from the same substrate was demonstrated: three foils could be lifted-off, one after the other, from the same parent substrate.

This development of the Slim-cut process was supported by the realization of simulation model at Armines. A static numerical approach was developed using finite element software, resulting in a model that is easy to use and can predict the depth of crack propagation depending on the epoxy thickness. Next to that, a monolithic method with a Lagrangian approach was introduced to model the 2D dynamic crack propagation of the Slim-cut process.

WP3: Gripping and handling development
Work package 3 and the according tasks aimed at the development of an automated approach for ultra-thin wafer handling. The transfer of thin wafers and the development of an appropriate handling technique were investigated first. The goal was to identify the additional challenges in terms of automated ultra-thin (<100 µm thickness) wafer handling. The benchmarking and evaluation of gripping principles and prototype grippers, as well as market products was performed and delivered. The gripper investigation and performance testing for mass manufacturing was ongoing in parallel. To do so, a setup and integration of a handling prototype based on a SCARA-robot for the ultra-thin wafer handling and precise module assembly was performed. Side by side with a prototypic position measurement system, the developed handling equipment demonstrates an integrated and automated process flow for ultra-thin wafers, able to interface with neighbouring processes.

The development of a gripping-mechanism for curled wafers was undertaken as well. A prototype gripper, a modified Bernoulli-gripper, has been designed, manufactured and tested for feasibility with curled wafers among other grippers.

Also to pick up a foil from a liquid, a gripping method was developed. Due to the advanced requirements of the handling situation in the liquid environment, a more systematic approach was developed for the testing of suitable gripping techniques. The process conditions of the dynamically changing liquid, such as contaminated solution or alcohol, require a certain automatic control system. This automated gripping-in-liquid was successfully demonstrated at Fraunhofer.

For the module level processing sequence the ultra-thin wafers need be placed on a silicone coated superstrate (bonding-on-glass) with high precision. The identification of positioning accuracies was one major challenge in this activity. A work piece carrier has been designed. A positioning accuracy of ~50 µm has been demonstrated.

The consortium had chosen for laser notches to create a starting position for crack propagation during the Slim-cut process. A Crack Initiation Module (CIM) with a micron resolution motorized xyz-stage and a nanoseconds pulsed fiber infrared laser was designed and realized by 4Pico in the course of the project. It was demonstrated that the CIM is able to create precisely parallel notches in silicon material. Successful lift-off is obtained on samples with these laser notches. Samples with these notches were used throughout the project for the development of the Slim-cut process in work package 2.

At AMAT several tests were performed regarding dispensing. For the dispensing of the silicone encapsulant, the installation of an automatic alignment system allowed a more accurate alignment. Dispensing this encapsulant was applied to fill the gap in between two wafers on a module. Tests showed that the shape and the thickness of the dispensed silicone depend strongly on the gap between the wafers.

WP4: Bonding and encapsulation
In this work package, the requirements for the adhesive and encapsulant were first identified, and a suited set of silicone materials (front adhesive, gap filler, rear encapsulant) was developed. The application of these materials to create the target structure was demonstrated.

A process to apply very uniform thin silicone layers (50 to 100 µm thick) on glass was developed and perfected, and a process sequence was established. A specific advantage of the method is that the silicone can be printed selectively, forming the desired pattern. The established process for wafer bonding consists in applying the silicone, curing the material, placing the wafer at the precise location, and applying a slight vacuum. With the appropriate silicone material and this method, large area wafers could be bonded to glass in a bubble-free structure.

Processes for precise placement of wafers on the silicone-covered glass were developed. There was both a lab process developed, but an automated pick-and-place process using a fast speed robot was demonstrated, even with very thin wafers. No issue were observed concerning breakage, and accurate and good bonding was achieved.

The rear encapsulation process was developed, which included the selection of the other materials needed to complete the laminate, in particular the backsheet.

A process for silicone dispensing for gap filling was developed and optimized.

Finally complete encapsulated devices were made combining the various developments in the work package, and the mini-modules were passed on to work package 6 for accelerated aging tests.

WP5: Processing steps for module level cell processing
The work performed in this work package was needed to develop all the processing steps to realize cells. In the envisaged process flow, the front side of the cell is processed first, followed by permanent bonding of this front side to a glass superstrate. After bonding, the remaining processing steps are executed while the partly processed cell is bonded to the superstrate.

Regarding the front side of the cell, a complete low-temperature (<250°C) technology, including texturing, passivation and anti-reflective coating, has been developed. The compatibility of this front-side processing with a temporary bonding method using a temporary adhesive has been studied.

In strong collaboration with work package 4, a flow has been developed that allows processing partly processed cells which are bonded to the glass. One of the main difficulties to overcome was the interaction between the silicone material used to bond the wafers and the subsequent PECVD depositions of a-Si:H. These silicone-plasma interactions lead to low quality of the a-Si:H deposition. At the end of the project, a flow overcoming this problem was demonstrated. In this flow, a blanket silicone layer was used to bond the wafers, omitting the need to pattern this silicone layer. Despite this blanket layer, interaction of the silicone with the plasma could be completely avoided by implementing the proper processing steps.

To realize the emitter and BSF regions at the rear of the cells, the consortium chose for doped a-Si:H as this is a low temperature process being compatible with the bonding. Within the project, a process flow was developed to realize interdigitated regions of n+ a-Si:H for the BSF and p+ a-Si:H for the emitter. This processed was demonstrated in functional devices with efficiencies up to 17.9%.

Also for the metallization of the cells a process needed to be developed. The consortium realized a metallization stack allowing contacting both a-Si:H emitter and a-Si:H BSF. The value of this stack was demonstrated in devices. Next to that, a method based on screen printing a low temperature Ag paste was developed to interconnect thin cells bonded to glass.

WP6: Characterization and reliability testing on module level
The stability of silicone encapsulation was investigated. The material turns out to have outstanding stability in various testing conditions. Modules made with traditional cells, but using silicone encapsulation instead of traditional encapsulants in a glass-encapsulant-backsheet structure showed superior stability in damp heat conditions.

Experiments at mini-module level were carried out using MWT cells bonded on glass using silicone and interconnected by soldering while bonded on glass showed that such structures could pass the reliability requirements in terms of damp heat and thermal cycling. The reliability of interconnection with low temperature metallization paste printed over a gap-filled trench also indicated that such structure did not degrade under damp heat and thermal cycling. Finally, an issue of instability in damp heat of amorphous Si passivating layers on wafers encapsulated in a glass-silicone-polymer backsheet was identified. Approaches to solve this problem were investigated, and solutions were found to avoid this degradation.

WP7: Integration, demonstration, concept and cost modelling
In this work package, several tasks related to demonstration and industrialisation of the cell concept, were grouped.

One of the constraints for the cell concept of the project is that after bonding the half-processed wafers on the glass superstrate, all processing steps need to be executed on the area of the glass, which can be a few m2. To demonstrate that this constraint is not a showstopper for the cell concept, the consortium developed and demonstrated a representative set of the processing steps on large-area superstrates. The involved steps include the deposition of silicones, the application of large area resist patterns and the deposition of a-Si:H layers on large areas.

To demonstrate the viability of the module level processing steps developed in work package 3, 4 and 5, being the application of the silicones, the precise placement of the cells and the metal interconnection between the cells, these steps were demonstrated with up scalable equipment at partner`s site. This resulted in a functional mini-module.

In terms of the development of a pilot line for Slim-cut manufacturing and the development of a concept for volume manufacturing, a detailed analysis of the process steps has been conducted in parallel to the continuous demonstration of single processes by each partner. Moreover, thanks to data collection and adaptation of a recent PV cost model, a comparison of Slim-cut based PV with standard PV could be calculated. Cost of one lift-of has been calculated to be 0.89 €/foil for a 156x156 mm2 foil.

Potential Impact:
The potential impact of the Sugar project is:

a. Solving the issue of availability of Si material of required quality
Sugar is almost fully dedicated to the more efficient use of the silicon solar-grade feedstock, both from the wafering, as from the module level processing perspectives. Four major features of the project foresee a more efficient use of silicon:
• The wafers produced by Slim-cut will be thinner.
• The wafers are produced with a much lower kerf loss.
• The solar cell process developed is amongst the most promising solar cell structure in development regarding conversion efficiency. Producing more cells with higher conversion efficiency also makes the use of silicon more efficient (less g/Wattpeak), regardless of the foil production method used.
• Part of the processing issues related to working with thin material will be solved, as dedicated thin film handling and operations will be developed, also regardless of the foil production method used.

b. Further reducing costs of solar modules
According to Crystal Clear, the module cost is indeed driven at 45% by the cost of a wafer. Coming to an accurate figure of the production cost of the solar cells with the proposed Slim-cut method is very delicate at the beginning of this very innovative project since the method diverges very much from what is currently proposed.
Still, as substantially more wafers can be gained out of the same ingot (3 versus 1 wafer for conventional wire sawing due to thinner wafers and less kerf loss), a strong potential to decrease wafer and as such module cost is present.
The techno-economical evaluation will be detailed as an output of Sugar. Envisaging industrialisation of the technology will not go without a cost study.

c. Accelerate the move to higher efficiency solar cells (>20%)
The most efficient industrial solar cells concepts are the interdigitated back-contact cells and the heterojunction cells. The process developed in Sugar is the combination of both technologies and carries therefore a very high efficiency potential.

d. Accelerate the move to thinner silicon wafers (<100 µm, and as thin as 50 µm)
Sugar is an ambitious project that integrates modifications of all the value chain of a PV module production line to propose a solution specifically adapted to ultra-thin wafer processing. Sugar proposes a method to obtain these thin Si foils and on top of that a method to produce them into modules with a very high efficiency potential.
The standard technology (wire sawing) has no potential for slicing 50-um thin wafers. The Slim-cut method proposed by Sugar is one of the few methods having this potential, and probably the one who carries the most cost-effectiveness potential
The industrial technology of today will not be able to process such wafers with acceptable yield. Sugar proposes a suitable technology based on processing on carriers. The wafers positioned on a glass carrier are processed into solar cell on module level. This technology therefore carries in addition a substantial cost-reduction potential, making it a very probable technology for the future.
These two technologies are developed simultaneously. This continuous survey ensures that the technology development will not be hindered by a delay in the development of another part of the technology: despite the noticeable synergies between the different Sugar technologies, the success and implementation to industry might come from any independently developed aspect of the technology.


Communication and dissemination
A public website of the Sugar project is available at https://projects.imec.be/sugar. Its content includes a general presentation of the project. Updates concerning public dissemination and events were made on a regular basis.

The consortium has published 15 scientific papers in peer-reviewed journals with results obtained within Sugar. Next to that, the consortium has presented 25 contributions at international conferences and workshops in the form of oral presentations and posters. Conferences included top conferences in the field such as the European Photovoltaic Solar Energy conference, the IEEE Photovoltaic Specialists conference and the MRS spring meeting. Moreover, at least three PhDs theses have been and will be defended on the research done within the Sugar project.

Exploitation
The Sugar project led to one patent application, which is joint patent between two partners of the consortium: Dow Corning and imec.
The main exploitable results generated by Sugar include:
• A Slim-cut process by an epoxy stress-inducing layer and with small thermal budget resulting in high quality Si foils
• A process flow to realize solar cells with on the rear an interdigitated pattern of an i/p+ emitter and an i/n+ BSF.
• A process flow which allows to process thin wafers bonded to glass.
• A printing technique to deposit very thin and uniform layers of silicone liquid encapsulant, which allows to bond thin wafers to glass in a bubble-free way.
• Laser assisted cutting of sharp notches in Si wafers, with a high precision and high repeatability.
• Handling and assembly process for accurate bonding-on-glass assembly of ultra-thin substrates
• Automated pick-and-place of sensitive substrates in liquid media with advanced process control
• Control of silicon substrate failure mechanism under thin films compressive loadings
• Crack propagation modelling under thermomechanical loading using a level-set framework and anisotropic mesh adaptation
• Dispensing of silicone encapsulants
• Printing of resist materials

List of Websites:

The address of the Sugar project website is: https://projects.imec.be/sugar

The list of main project contacts is:
• imec - coordinator: Maarten Debucquoy, maarten.debucquoy@imec.be Tel: +32 16 287593
• Armines: Marc Bernacki, marc.bernacki@mines-paristech.fr
• Fraunhofer: Tim Giesen, tim.giesen@ipa.fraunhofer.de
• Ferro: Peter Van Eijk, peter.vaneijk@ferro.com
• Dow Corning: Guy Beaucarne, guy.beaucarne@dowcorning.com
• AMAT: Alessandra Querci, alessandra_querci@amat.com
• FFCUL: João Manuel de Almeida Serra, jmserra@fc.ul.pt
• Semilab: Miklos Tallian, miklos.tallian@semilab.hu
• 4Pico: Hendrik Postma, hendrik@4pico.nl
• Ferro Hanau: Barbara Adrian, barbara.adrian@ferro.com

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