Objetivo
A current steering Digital to Analog Converter (DAC) is the enabling integrated circuit for high-speed waveform generation, with key applications such as UMTS cellular base stations, DOCSIS compliant digital TV broadcast, and RF test equipment. There is continuous demand for higher speed and higher resolution DACs that can generate waveforms at higher output frequencies with good linearity.
The most important linearity metric of a high speed DAC is Spurious Free Dynamic Range (SFDR), and other measures such as Intermodulation Distortion (IMD) or Adjacent Channel Leakage Ratio (ACLR) depend on SFDR. Even with the state of the art DACs, SFDR drops very fast with increasing output frequency. Best 16-bit, high-speed DACs can achieve 95 dB SFDR at Fout = 1MHz, however, SFDR drops to less than 70 dB at Fout > 100 MHz. To generate more accurate waveforms at high frequencies, it is crucial to identify, understand and address the dynamic error mechanisms of DACs.
In a nutshell, the project proposal consists of identification, avoidance and elimination of dynamic error mechanisms, demonstrated by a 16-bit, 2 Giga-sample-per-second (GSPS) DAC , on a 0.18u CMOS process. The focus will be on switch design, clock network design, output network design, switching algorithm design and built in self-test (BIST) structures. VLSI design tools and test equipment will be provided by Istanbul Technical University. Project funds will be used to support two researchers and, and multiple shuttle tape-outs. The project coordinator is familiar with the real technical issues involved, he has 13 years of industry experience in DAC testing, DAC design, and DAC design management at prestigious US corporations such as Texas Instruments and Linear Technology. He released numerous DACs to production and he has many refereed publications and patents on DAC design.
Convocatoria de propuestas
FP7-PEOPLE-2010-RG
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Régimen de financiación
MC-IRG - International Re-integration Grants (IRG)Coordinador
34469 Maslak, Istanbul
Turquía