Final Report Summary - REACT (Rare Earth Oxide Dielectrics for Advanced Germanium CMOS Technology)
High mobility Germanium is thought to be a new important introduction in critical parts of the next generation transistor devices. These types of devices are expected to find their use in applications where high performance and low power operation are both needed. These cover sectors in multimedia and mobile internet (tablets, smart phones etc) which heavily rely on battery lifetime. The aforementioned products are widely used by the consumers and are essential to our society. People will continue enjoying improved mobile products and services at ever reducing costs provided that the power consumption and heat generation on the chip is controlled (thanks, in part, to advanced CMOS with high mobility channels) at reasonable levels to allow further miniaturization and higher frequency operation. However bringing Ge in production is not an easy accomplishment. The biggest problem is that nMOS Ge underperforms and the question about the reason why this happening still remains open. To compensate for Ge nMOS underperformance researchers and technologists around the work are looking for other solutions like the dual channel p-Ge/n-InGaAs CMOS which however has big integration problems on large area Si substrates. A fully Ge-CMOS technology would be preferred if the problem of Ge n MOS is made to work properly. It is not known at present what causes the Ge nMOS underperformance. Our previous proposal that native dangling bond defects near the VB maximum of Ge could play a role in mobility reduction is an explanation. The puzzling thing though is that some gate dielectrics (especially the rare earth oxides) passivate the interface defects, including the dangling bonds sufficiently as can be inferred from the capacitance voltage and conductance voltage measurements in Ge capacitors. However, when one tries to make transistor devices, the results especially for nMOSFETs are poor. This indicates that it is not the interface defects or dangling bonds that limit the mobility but some other type of defects. In REACT we investigated the interaction of the cations in the gate oxide with oxygen and native defects in Ge and we found that they form stable defect complexes residing in the Ge channel potentially acting as charge scatterers with deleterious effects in the mobility and the drive current of MOSFETs. One way to avoid the deleterious effects of cations-oxygen native Ge defect complexes, is to separate any high-k metal oxides from the Ge channel by inserting on purpose an ultrathin GeO2 which acts as very good passivation layer however not with every high-k dielectric but only when it is combined with either Al2O3 or Y2O3 oxides. In fact, using Y2O3/GeO2 and Al2O3/GeO2 gate stacks the best transistor results have been reported by others in the literature. In REACT, we investigated these gate stacks and came to the conclusion that Al and Y diffuse into the underlying ultrathin GeO2 layer and passivate the oxygen vacancy defects in GeO2 because they are tri-valent and eliminate defect states from the gap. We call this the “valence passivation” effect. Other cations like Hf are not equally effective because as they have different valency. Our work could explain the success of Y2O3/GeO2 and Al2O3/GeO2 gate stacks in Germanium capacitors and transistors.
Summarizing, in REACT we studied in depth some of the problems associated with the gate dielectrics in Ge MOS capacitors and transistors and we have proposed possible reasons for their underperformance when the dielectrics are in direct contact with the Ge channel. We also suggested what would be the reason for the success of a couple of successful gate stacks in terms of valency passivation. Our results could be useful to materials scientists, electrical engineers and semiconductor technology developers who could benefit from the knowledge created to better understand why some gate stack solutions are better than others and how they can further improve their process modules to achieve performing devices for the next generation computer chips.
Summarizing, in REACT we studied in depth some of the problems associated with the gate dielectrics in Ge MOS capacitors and transistors and we have proposed possible reasons for their underperformance when the dielectrics are in direct contact with the Ge channel. We also suggested what would be the reason for the success of a couple of successful gate stacks in terms of valency passivation. Our results could be useful to materials scientists, electrical engineers and semiconductor technology developers who could benefit from the knowledge created to better understand why some gate stack solutions are better than others and how they can further improve their process modules to achieve performing devices for the next generation computer chips.
