Final Report Summary - SMARTGATE (Smart Gates for the "Green" Transistor) II-Publishable Summary-Two dimensional (2D) materials for energy efficient nanoelectronicsIn the last decade the world has experienced the convergence of multimedia to a single mobile internet device the most successful example being the smartphone, which combines computing, video recording and gaming with mobile wireless communication. What has enabled this progress is the availability of suitable technology to provide high performance at low power supply voltage (Vdd), in other words to combine high performance with low power operation. At present we are entering a new era where the technology diversifies again into a number of smart devices with Internet connectivity which we often call “the Internet of Things (IoT)”. The most important requirement for the IoT is ultra-low power consumption in order to face the challenge of device operation with limited battery resources, without compromising performance. Low power operation though is a more general requirement in the area of nanoelectronics, since excess heat on the chip degrades performance and eventually inhibits dimensional scaling. Moreover the large amount of data processed and stored in big data servers consumes a large part of energy resources in technologically developed countries affecting energy autonomy and security. In general, there is a large demand for energy savings in all sectors, including electronics, for a greener economy.There are several ways to face the challenges in the struggle for energy efficient nanoeletronics at the circuit and device architecture levels as well as the materials level. The main effort is on steep slope switches featuring subthermionic transport with subthreshold slope (SS) less than the thermal limit of 60 mV/dec. The most popular has been the development of tunneling field effective transistor (TFET) architecture which provides very low current in the OFF state and steep slope switching but suffers from low current in the ON state, which makes them not very suitable at present for high performance applications. In SMARTGATE, among other things we investigated the possibility of using van der Waals heterostructures of 2D metal dichalcogenide semiconductors to fabricate 2D-2D vertical TFETs. We have experimentally identified the right materials combination with favorable band alignment which allows the fabrication of (nearly) broken gap vertical TFETs creating the prospect for uninhibited large current in the ON state through a small van der Waals gap at the heterointerface. Another route to obtain step slope switching is to fabricate negative capacitance FET (NCFET) devices. The latter devices are considered serious contenders of TFETs and are rapidly gaining momentum since the recent demonstration of NC(fin)FETs (IEDM 2015) with Hf-based ferroelectric oxide dielectrics and with SS smaller than the thermal limit. This progress has ignited an immense interest and NCFETs are now included in the 2015 edition of the ITRS roadmap. Despite this success, NCFETs with ferroelectric gates suffer from hysteresis and depolarizing fields which render their operation unstable which in turn leads to performance degradation. There are also concerns about speed of these devices due to rather slow ferroelectric domain switching while scalability to very low EOT without harming ferroelectricity and NC effect is questionable. To overcome the shortcomings of ferroelectric-based NCFETs, in SMARTGATE project we adopted a radically different approach in which we integrated one monolayer of graphene in the gate of field effect devices. Using graphene-based metal insulator-semiconductor devices with graphene-based gates we showed that an internal gate amplification can be obtained as a result of the negative quantum capacitance of graphene arising from electron-correlation effects. The work was published and featured in the April issue of Advanced Electronic Materials. In addition, we found that “as-is” MOSFET transistors with graphene-based gates are superior to control devices exhibiting steeper slopes but not steeper than thermal limit possibly due to inefficient passivation of interface defects. Graphene-based NCFETs are scalable to large area wafers and the NC effect is improved with gate dielectric scaling. Moreover, the graphene-based gate stacks are compatible with several channel materials and device architectures (Si, Ge, III-V, SOI) and they are symmetric source-drain devices taking full advantage of the high current in the ON state that can be obtained in state of the art MOSFET devices. Therefore NCFETs including graphene-based NCFETs show good prospect for manufacturable device technology which could deliver both low power and high performance for mobile internet device applications and the IoT.
