Skip to main content

Conduction Mechanisms in Advanced MOS Technologies

Final Report Summary - CONAT (Conduction Mechanisms in Advanced MOS Technologies)

Silicon-based transistor technologies are approaching the physical limits of miniturisation. Significant technology breakthroughs, in terms of materials and processes, will be required as device sizes reach the nano-scale frontier. To face these challenges, a new generation of devices based on a clever combination of selected materials is currently under consideration worldwide. Devices fabricated from III-V compound are being considered due to high electron mobility and the availability of semi insulating substrates. However, a significant factor that has inhibited the wide use of such materials is the lack of stable high quality gate insulators on III-V channels. Improving the understanding of degradation mechanism in this novel stacks is the primary obstacle to the successful incorporation into the mainstream semiconductor process.
The aim of this project was to investigate the degradation and breakdown characteristics, of Metal Gate/High-K structures on III-V substrates intended for applications in future MOS transistors. The work carried out to achieve this objective was focused in obtain experimental data to understand the limiting factors and the dynamics of degradation of such stacks. The methodological approach has combined the electrical characterization with a deep analysis on the composition of the interface.
In order to implement the project I have collaborated with my host researcher, Prof. Moshe Eizenberg, and the PhD students of his group, the Electronics Material Group, in the Materials Science and Engineering Department of the Technion-Israel Institute of Technology (Haifa). The facilities at the Electronics Materials group have been used for the electrical characterization of the devices, while the facilities of the Department of Materials Science and Engineering, and of the Nanotechnology Center have been used to characterize the structure and for the fabrication of the devices respectively.

InGaAs is an attractive candidate to be used as a channel material beyond Si thanks to its high electron mobility. Lacking a good native oxide interface, a major challenge in using it is the characterization and the understanding of the various defects components that affect the high-k dielectric/InGaAs performance and long term reliability. Our results has showed that the defects related to the characteristics of the InGaAs substrate play a major role in the degradation characteristics of the stack. Moreover, it has been shown that the degradation, particularly under negative bias, is strongly affected by the oxide-semiconductor surface treatment of the samples. A better quality of the interface in term of interface states; contributes with larger amount of charge on the dielectric layer. The simultaneous generation of positive charge and interface states suggest that depassivation of the interface is the main mechanism for the generation of positive charge. The overall results clearly show that the improvement of the high-k dielectric/InGaAs interface doesn't necessarily mean an increase of the reliability of the MOS stacks.

The physical damage associated with gate-oxide breakdown (BD) has also been a topic of this research project. We have been studied it in order to understand and model the failure mechanisms that affect the performance of devices fabricated from high-k dielectrics/III-V stacks. In advanced complementary metal-oxide-semiconductor (CMOS) circuits, the BD of gate dielectrics occurs in the regime of relatively low voltage and very high electric field. Such BD is characterized by a gradual, progressive growth of the gate leakage through a localized BD spot. We have demonstrated the ability to control the breakdown growth rate of a number of gate dielectrics and provide a physical model of the observed behavior, allowing to considerably improve the reliability margins of CMOS circuits by choosing a correct combination of voltage, thickness, and thermal conductivity of the gate dielectric.

The post-breakdown characteristics of metal gate/Al2O3/InGaAs structures were also studied using surface analysis by X-ray photoelectron spectroscopy (XPS). The results show that for dielectric breakdown under positive bias, localized filaments consisting of oxidized substrate atoms (In, Ga and As) were formed, while following breakdown under negative bias, a decrease of oxidized substrate atoms was observed. Such differences in the microstructure at the oxide-semiconductor interface after breakdown for positive and negative voltages are explained by atomic diffusion of the contact atoms into the gate dielectric in the region of the breakdown spot by the current induced electro-migration effect. These findings show a major difference between Al2O3/InGaAs and SiO2/Si interfaces, opening the way to a better understanding of the breakdown characteristics of III-V complementary-metal-oxide-semiconductor technology (III-V CMOS).

This project has improved the knowledge to define advantages and limiting factors of the application of III-V CMOS technology in terms of its reliability.
Leading the transition to advance electronics is a challenge for applied research which has to set up the required technology platforms. It is in this aspect that this project has contributed to enhance the excellence in the European Research Area in connection with the interest of the industrial sector of nano-technology.
I anticipate the collaborations conducted during this project to be a significant stepping stone in my independent academic career. Specifically, the research project will elaborate lasting-collaborations that I will continue to cultivate afterwards.