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Specialisable, Programmable, Efficient and Robust Microprocessors

Objective

The development of faster, cheaper and smaller transistors has been the driving force behind the exponential growth in computing power over the past 50 years. While our ability to fabricate better transistors has not yet ceased, continuing to translate these advances into better system-level performance is now a major challenge. This proposal seeks to research a new approach to building programmable digital systems, one that can offer the efficiency, robustness and flexibility required as we approach the end of the CMOS era and start to introduce new post-CMOS technologies. The ideas are centred upon a novel network-centric multiprocessor architecture, with contributions planned at every level from the circuit to the language level.

Call for proposal

ERC-2012-StG_20111012
See other projects for this call

Funding Scheme

ERC-SG - ERC Starting Grant

Host institution

THE CHANCELLOR MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE
Address
Trinity Lane The Old Schools
CB2 1TN Cambridge
United Kingdom
Activity type
Higher or Secondary Education Establishments
EU contribution
€ 1 271 216
Principal investigator
Robert Mullins (Dr.)
Administrative Contact
Renata Schaeffer (Ms.)

Beneficiaries (1)

THE CHANCELLOR MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE
United Kingdom
EU contribution
€ 1 271 216
Address
Trinity Lane The Old Schools
CB2 1TN Cambridge
Activity type
Higher or Secondary Education Establishments
Principal investigator
Robert Mullins (Dr.)
Administrative Contact
Renata Schaeffer (Ms.)