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Content archived on 2024-06-18

Innovative Reliable Chip Designs from Low-Powered Unreliable Components

Project description


Challenging current Thinking

The ongoing miniaturization of data processing and storage devices and the imperative of low-energy consumption can only be sustained through low-powered components. Lower supply voltages and variations in technological process of emerging nanoelectronic devices make them inherently unreliable. As a consequence, the nanoscale integration of chips built out of unreliable components has emerged as one of the most critical challenges for the next-generation electronic circuit design. To make such nanoscale integration economically viable, new solutions for efficient and fault-tolerant data processing and storage must now be invented. The i-RISC project aims at achieving these goals, by providing innovative fault-tolerant solutions at both device- and system-level that are fundamentally rooted in mathematical models, algorithms, and techniques of information theory. Proposed solutions will build on error correcting codes and encoder/decoder architectures able to provide reliable error protection even if they themselves operate on unreliable hardware. The project will develop the scientific foundation and provide a first proof-of-concept by validating the proposed solutions on accurate error models and energy measurement tools developed within the project. In the forthcoming challenge of nanoscale technologies, the i-RISC project is an essential prerequisite for preparing the European industry for this paradigm shift.

Fields of science (EuroSciVoc)

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Programme(s)

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Topic(s)

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Call for proposal

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FP7-ICT-2011-C
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Funding Scheme

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CP - Collaborative project (generic)

Coordinator

COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
EU contribution
€ 455 098,00
Address
RUE LEBLANC 25
75015 PARIS 15
France

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Region
Ile-de-France Ile-de-France Paris
Activity type
Research Organisations
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Total cost

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Participants (5)

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