Final Report Summary - RESACC (Development of a readout circuit for a resonant accelerometer)
Executive Summary:
The goal of this project was the development of an ASIC to interface a resonant MEMS developed by Thales in order to miniaturize, reduce power consumption and reduce cost of a system offering inertial grade performances.
The consortium built to develop this ASIC is composed of CSEM and HMT. They both come from Switzerland, with strong R&D and industrialization experience in the area of high-performance ASICs, and already having experience working together on innovative sensor-ASIC projects and products.
The ASIC developed within the project incorporates the main functions to drive the resonant MEMS:
• A main oscillation loop implemented by a transimpedance amplifier, a variable gain and a MEMS driver.
• A secondary amplitude control loop which fixes the level of the sensed signals.
• A damping loop built with another transimpedance amplifier, a bandpass filter and an output buffer, to damp the mechanical energy of the proof mass.
• A digital block incorporating configuration registers as well as counters to digitize the acceleration measurement based on a counting scheme. It also incorporates a serial interface (SPI) to communicate with an external device.
• Different peripheral blocks
The ASIC is realized in a 350 nm process with high voltage options, as voltages in excess of 10 V are required for the damping of the proof mass. A first version was integrated and characterized.
This ASIC enables the reduction of the volume and power consumption of high performance resonant accelerometers, opening the door for the widespread dissemination of such products throughout the avionics field, and especially for integrated flow and load control systems as applied to the wings of civil aircraft.
The first generation of the ResAcc ASIC was realised within the scope of the ResAcc project on a multi-project wafer run. This ASIC demonstrated satisfactory functional, noise and temperature stability performance and also served as a proof of concept for the system including the MEMS. Problems with the ASIC are, however, observed due to packaging parasitics, amplitude control, and gain mismatch between design and measurement.
A second generation ResAcc ASIC was planned during the project. Due to the increased effort required to develop the first generation, and various delays this was not possible before the end of the project. The project partners are, however, continuing to develop the second generation ASIC, with which we expect to solve the observed issues.
Project Context and Objectives:
Up to now, most of MEMS based accelerometers are capacitive, sensing the capacitance change of a proof mass induced by acceleration. However, this type of accelerometer suffers from drift in the presence of radiation, thus preventing their use in space applications or harsh environments. Another class of MEMS accelerometers measures the resonant frequency of a proof mass which changes with the acceleration. Such accelerometers are not affected by radiation. However their resonant frequency is dependent on temperature. In order to suppress this dependency, resonant accelerometers make use of 2 resonators whose respective resonant frequency have positive and negative dependence to temperature. Acceleration is thus measured by sensing the difference in resonant frequency of the 2 resonators.
The main objective of the project was the development of a readout interface for the resonant accelerometer developed by Thales and referred under Accix A-HP-10 in the call for proposal CS-2012-01-SFWA-01-046 named “MEMS Accelerometer – Miniaturisation of the analogue electronics in an Asic”. Its goal is to offer a low cost fully integrated and reliable solution compatible with inertial grade performances. Up to now, very few integrated readout circuits for resonant accelerometers have been demonstrated, furthermore these circuit do not deliver a digital representation of the acceleration. The current project adopted a system-on-chip approach by combining on a single chip the sensor interface and the measurement of the frequency shift induced by the acceleration in order to deliver a digital representation of the acceleration.
The present project innovates with respect to several points:
• Combined analog sensor interface and digital output on a single chip,
• Simultaneously high resolution and high bandwidth,
• On-chip high accuracy amplitude control,
• On-chip damping loop,
• Low power consumption.
Table 1 lists the main specifications.
Consortium
The ResAcc consortium is multidisciplinary, with the two partners coming from Switzerland, with strong R&D and industrialization experience in the area of high-performance ASICs, and already having experience working together on innovative sensor-ASIC projects and products.
CSEM is an independent research and development company, partially funded by the Swiss confederation. Established in 1984, CSEM (Centre Suisse d’Electronique et de Microtechnique SA) is a private R&D centre specializing in microtechnology, nanotechnology, microelectronics, systems engineering and communications technologies. It provides its industrial customers and partners with tailored, innovative R&D and product development services based on its commercial and technological expertise, further expanded by the results of its applied research. Additionally, through the establishment of start-up businesses, it actively contributes to developing Switzerland as a centre of industry and commerce.
Active in the ASIC and microelectronic module design industry since 1978, HMT is one of Europe’s largest independent contract design houses. HMT’s dynamic team of engineers is dedicated to customer developments and industrialization of those, comfortably providing the capacity for complex projects in the mixed signal field. Besides HMT’s positioning in the ASIC field, HMT is since 1988 active in module technologies of miniaturization projects.
Project organization
The project was coordinated by CSEM. CSEM was in charge of the oscillator loop design, the digital design and the top level assembly, whereas HMT was in charge of the damping loop and high voltage block design. The overall project is supervised by Thales, the Topic Manager.
Figure 1 shows the work packages organization of the project.
The work is divided within 5 work packages:
WP1 concerns the specification and the characterisation strategy of the ASIC. The goal of this WP is to establish detailed design specifications of each block constituting the ASIC. This WP is very important to enable a smooth execution of the ASIC design (WP2).
WP2 deals with the design of the ASIC starting from the specifications and ending with the layout and the characterisation plan of the ASIC ready for integration. It consists in the design and simulation of each blocks constituting the ASIC, the system design and simulation to assemble the different blocks into a coherent ASIC, and finally the realization of the layout of the ASIC.
WP3 concerns the characterization of the ASIC at laboratory level according to a pre-established characterization plan. For this purpose, a dedicated PCB is designed and realized during the integration of the ASIC.
WP4 deals with the activities concerning dissemination and exploitation of research results produced within this project, attempting to maximize the knowledge transmitted from this research project to the scientific and the industrial world working on aeronautics.
WP5 contains the management activities, including administrative tasks and reporting, but most importantly ensuring the correct planning and execution of the project to achieve the technical objectives within the set deadlines and budget.
Project Results:
This section describes the main scientific and technical results of the ResAcc project. The goal of the project was the design of the ResAcc ASIC to interface the resonant MEMS developed by Thales.
Global architecture
The architecture of the chip is based on user requirements provided by Thales, which also includes different peripheral blocks. It is important to note that the ResAcc ASIC designed in the ResAcc project framework integrates only a part of the complete system that is targeted by Thales. Figure 2 shows a block schematic of the MEMS, the ResAcc ASIC to be designed (in grey), and additional blocks (in orange). The blocks to be integrated on the ASIC are considered as the most critical ones. The other blocks will be external components within the ResAcc project, but will be integrated on chip beyond the ResAcc project to lead to a sensor interface with a minimal count of external components.
The MEMs is composed of 2 resonators, which resonant frequencies are a function of the force transmitted to them by a seismic mass. The principle consists first of sensing the capacitance change of the resonators and amplifying it to a suitable voltage. This voltage is then used for 3 purposes:
• it is fed back through an analog loop to excite the resonator with a suitable amplitude.
• it enters a trigger detection block to enable on-chip digitalization of the acceleration based on a counting scheme.
• it can be digitized by an off-chip ADC for further processing to enable a more precise computation of the acceleration.
The electronics + the resonator are basically an oscillator locked to the resonant frequency of the MEMS resonator. Input acceleration modifies the resonant frequency and also the oscillator frequency. The oscillator frequency is then to be converted into digital information through counting techniques or more sophisticated signal processing algorithms.
The C/V converter is composed of a transimpedance amplifier. The output of the transimpedance amplifier is amplified and fed to the amplitude control loop, an analog buffer to output the analog signal on pads, and a trigger to digitize the analog signal by detecting its zero-crossings.
The amplitude control block extracts the signal amplitude after amplification and full-wave rectification and compares it to a voltage reference. The difference between the sensed amplitude and target is integrated to control the variable gain of the driver.
A damping block provides active electrostatic damping of the seismic mass through sense and drive electrodes.
Acceleration computation principle
The difference in frequency of the two resonators can be measured very easily by counting the number of periods of each resonator during a given time window and taking the difference between the counts. However, as resonant accelerometers have a sensitivity of a few 10s of Hz per g, this approach necessitates very long time windows to reach a high resolution.
It is not sufficient to use zero-crossings to achieve the desired resolution of 0.2mg at the signal bandwidth of 5kHz. Here a different technique is employed. The whole waveform of the resonator is digitised and the frequency shift measurement is performed in the digital domain with a resolution far lower than a full oscillation cycle.
The aim of the project is to develop a sensor interface performing on-chip digitization of the acceleration for low bandwidth and/or low resolution based on a counting scheme, and enabling off-chip computation of the acceleration based on digitalizing the whole waveform when higher performances (bandwidth, resolution) are needed.
Chip layout
Figure 3 shows an image of the layout of the first generation ResAcc ASIC, with the main blocks highlighted. The pad-ring is separated into 2 parts: a digital pad-ring on the left connecting the digital block, and an analog pad-ring on the right. The chip area is 9.3 mm2.
Characterisation set-up
To characterize the ResAcc ASIC, a PCB was developed, which main components are the ResAcc ASIC, the Thales MEMS and a microcontroller to handle data transfer between a PC and the ResAcc ASIC.
Figure 4 shows a picture of the PCB front-side with the ResAcc ASIC position highlighted by a red circle. The PCB holds sockets for the MEMS cell and the ResAcc ASIC to enable easy exchange of these components. Figure 5 shows the PCB backside with the socket to hold the Thales cell highlighted by a red circle. An NXP microcontroller is embedded on the PCB, managing reset sequence, clock generation and the SPI interface with the ResAcc chip. Dedicated firmware for the microcontroler have been developed and validated, allowing high speed SPI exchange. A Python graphical user interface has been developed to enable communication between a PC and the ResAcc ASIC. The graphical user interface enables to control all the registers of the ResAcc ASIC.
Results
The following section provides summary results from the characterisation of the first generation ResAcc ASIC. The ASIC demonstrated satisfactory functional, noise and temperature stability performance and also served as a proof of concept for the system including the MEMS. The full results are reported in the characterisation report.
Issues
Problems with the first generation ResAcc ASIC are observed due to:
• capacitive coupling due to packaging parasitics,
• function of the amplitude control loop
• slow startup behaviour
• gain mismatch between design and measurement in the main oscillators
• gain mismatch between design and measurement in the damping loop
• frequency offset of the damping loop filter transfer function
Power consumption
The power consumption with a 3.3 V supply voltage is slightly below 40 mW.
Main oscillator loop
The transfer function of the main oscillator loop is illustrated in Figure 6 for different value of Vgate, the voltage which controls the attenuation of signal EXC. At low attenuation (Vgate close to 0 V), the transfer function is quite flat up to the cut-off frequency. When the attenuation increases, a peak appears in the transfer function around 400 kHz. This peak is caused by parasitic couplings between the highly sensitive input of the transimpedance amplifier (pad DET) and the excitation pad (pad EXC). At high attenuation of the transimpedance amplifier output, the oscillator tends to lock on this frequency instead at the nominal resonant frequency of the MEMS around 45 kHz, thus preventing a correct functioning of the system.
Simulations of the transfer functions taking into account the injection network, and estimated parasitic couplings between pads internally to the ASIC as well as external couplings and parasitics have been performed. These have shown that the behaviour is related to external package and PCB parasitics and is expected to be corrected with the revised packaging of the second generation.
Figur 7 shows the transfer function of the main oscillator loop for 3 different temperatures (-40 °C, 25 °C and 85 °C) and 3 different gain settings of the transimpedance amplifier. The open loop gain drops by about 10 dB when the temperature increases from – 40 °C to 85 °C.
Damping loop
Figure 8 demonstrates the transfer function of the damping loop for different gain configurations, as measured by Thales. The centre frequency is lower than designed, and the absolute gain is also lower than targeted for the application. These effects are still under investigation.
Charge pump
Figure 9 shows the performance of the integrated charge-pump and regulator and their sensitivity to the pumping clock frequency (MCLK), where the nominal clock frequency is 40MHz. The target voltage and output regulation of the regulator at low loads meet the specification and match with the simulations.
The knee-point (eg. blue, nominal curve at 30µA) shows the point where the internal regulator no longer has sufficient head-room from the charge-pump to regulate correctly.
Startup
Figure 10 shows the start-up of the oscillator. Signal Vgate is maintained at 2 V during 20 s to ensure that the system (MEMS + ASIC) completely stopped oscillating. Then, Vgate is set to 0 V and the time necessary to obtain an oscillation amplitude of 100 mV is measured. Start-up time depends mainly on the setting of the transimpedance amplifier gain, varying between 2.5 s and nearly 13 s. Start-up time is much longer than what was specified (0.5 s). This is due to an insufficient gain of the transimpedance amplifier. In the second version of the ASIC, the gain of the transimpedance amplifier has been increased by a factor 9.
System proof of concept
Figure 11 shows the waveform measured on pads EXC1 and OSCP1 in closed loop (including the MEMS sensor) with an external control of the oscillation amplitude. The frequency is 44541 Hz.
Figure 12 shows the waveform on pads EXC1 and OSCP1 with internal control of the amplitude, obtained by averaging to filter some instability of the Vgate voltage.
Figure 13 shows the signals on pad EXC and OSCP as well as the Vgate voltages for the 2 oscillators of a same chip, without any averaging. The disphony between the 2 channels is -38 dB.
Project continuation
A second generation of the ResAcc ASIC is in development which is expected to correct the observed issues. Although foreseen within the scope of the ResAcc project, part of the development and all of the characterisation of this second generation will be conducted following the project. The positive results of the first generation, especially with respect to the major concerns of noise and temperature stability, give confidence in achieving the design goals with the second generation.
Potential Impact:
The ResAcc project has delivered an integrated sensor interface for a resonant MEMS. The first version of the ASIC exhibits several problems. However they have been identified and corrected on the second version, which will provide a basis to develop an industrial version offering inertial grade performances. This enables miniaturization, power consumption reduction and cost reduction of these accelerometers, which will allow for the widespread use of these products throughout the avionics field.
The continuation of the development of a product ASIC following the characterisation of the second ResAcc generation is planned between the ResAcc project partners and the Topic Manager.
This product ASIC will incorporate further auxiliary functions, including power management, a quartz oscillator and a temperature sensor with ADC, EEPROM and a revised digital functionality.
HMT and CSEM are employing the low-noise design techniques developed in this 0.35µm process in a number of unrelated and non-conflicting projects, primarily also in the sensor domains.
Beyond ResAcc, a variety of technical fields and market segments can be addressed by the project results and the know-how generated by the project. Indirect re-use of the project results can be considered with new projects for CSEM’s Swiss and industrial customers in fields such as:
• The construction segment, where accelerometer based sensor interfaces can be deployed to monitor structural health of the large buildings, bridges, tunnels, etc.
• The automotive field, where sensors and interfaces are taking increasingly larger roles for the driver and passenger safety and comfort.
• The machine industry where miniaturized sensors and sensor interfaces allow efficient monitoring and maintenance.
• The sports/wellness and medical/health segment, where accelerometer based sensor interfaces enable novel products for monitoring the motions of persons for real-time monitoring systems.
List of Websites:
www.resacc-project.eu
Pierre-François Rüedi, CSEM S.A. rue Jaquet-Droz 1, 2002 Neuchâtel Switzerland
The goal of this project was the development of an ASIC to interface a resonant MEMS developed by Thales in order to miniaturize, reduce power consumption and reduce cost of a system offering inertial grade performances.
The consortium built to develop this ASIC is composed of CSEM and HMT. They both come from Switzerland, with strong R&D and industrialization experience in the area of high-performance ASICs, and already having experience working together on innovative sensor-ASIC projects and products.
The ASIC developed within the project incorporates the main functions to drive the resonant MEMS:
• A main oscillation loop implemented by a transimpedance amplifier, a variable gain and a MEMS driver.
• A secondary amplitude control loop which fixes the level of the sensed signals.
• A damping loop built with another transimpedance amplifier, a bandpass filter and an output buffer, to damp the mechanical energy of the proof mass.
• A digital block incorporating configuration registers as well as counters to digitize the acceleration measurement based on a counting scheme. It also incorporates a serial interface (SPI) to communicate with an external device.
• Different peripheral blocks
The ASIC is realized in a 350 nm process with high voltage options, as voltages in excess of 10 V are required for the damping of the proof mass. A first version was integrated and characterized.
This ASIC enables the reduction of the volume and power consumption of high performance resonant accelerometers, opening the door for the widespread dissemination of such products throughout the avionics field, and especially for integrated flow and load control systems as applied to the wings of civil aircraft.
The first generation of the ResAcc ASIC was realised within the scope of the ResAcc project on a multi-project wafer run. This ASIC demonstrated satisfactory functional, noise and temperature stability performance and also served as a proof of concept for the system including the MEMS. Problems with the ASIC are, however, observed due to packaging parasitics, amplitude control, and gain mismatch between design and measurement.
A second generation ResAcc ASIC was planned during the project. Due to the increased effort required to develop the first generation, and various delays this was not possible before the end of the project. The project partners are, however, continuing to develop the second generation ASIC, with which we expect to solve the observed issues.
Project Context and Objectives:
Up to now, most of MEMS based accelerometers are capacitive, sensing the capacitance change of a proof mass induced by acceleration. However, this type of accelerometer suffers from drift in the presence of radiation, thus preventing their use in space applications or harsh environments. Another class of MEMS accelerometers measures the resonant frequency of a proof mass which changes with the acceleration. Such accelerometers are not affected by radiation. However their resonant frequency is dependent on temperature. In order to suppress this dependency, resonant accelerometers make use of 2 resonators whose respective resonant frequency have positive and negative dependence to temperature. Acceleration is thus measured by sensing the difference in resonant frequency of the 2 resonators.
The main objective of the project was the development of a readout interface for the resonant accelerometer developed by Thales and referred under Accix A-HP-10 in the call for proposal CS-2012-01-SFWA-01-046 named “MEMS Accelerometer – Miniaturisation of the analogue electronics in an Asic”. Its goal is to offer a low cost fully integrated and reliable solution compatible with inertial grade performances. Up to now, very few integrated readout circuits for resonant accelerometers have been demonstrated, furthermore these circuit do not deliver a digital representation of the acceleration. The current project adopted a system-on-chip approach by combining on a single chip the sensor interface and the measurement of the frequency shift induced by the acceleration in order to deliver a digital representation of the acceleration.
The present project innovates with respect to several points:
• Combined analog sensor interface and digital output on a single chip,
• Simultaneously high resolution and high bandwidth,
• On-chip high accuracy amplitude control,
• On-chip damping loop,
• Low power consumption.
Table 1 lists the main specifications.
Consortium
The ResAcc consortium is multidisciplinary, with the two partners coming from Switzerland, with strong R&D and industrialization experience in the area of high-performance ASICs, and already having experience working together on innovative sensor-ASIC projects and products.
CSEM is an independent research and development company, partially funded by the Swiss confederation. Established in 1984, CSEM (Centre Suisse d’Electronique et de Microtechnique SA) is a private R&D centre specializing in microtechnology, nanotechnology, microelectronics, systems engineering and communications technologies. It provides its industrial customers and partners with tailored, innovative R&D and product development services based on its commercial and technological expertise, further expanded by the results of its applied research. Additionally, through the establishment of start-up businesses, it actively contributes to developing Switzerland as a centre of industry and commerce.
Active in the ASIC and microelectronic module design industry since 1978, HMT is one of Europe’s largest independent contract design houses. HMT’s dynamic team of engineers is dedicated to customer developments and industrialization of those, comfortably providing the capacity for complex projects in the mixed signal field. Besides HMT’s positioning in the ASIC field, HMT is since 1988 active in module technologies of miniaturization projects.
Project organization
The project was coordinated by CSEM. CSEM was in charge of the oscillator loop design, the digital design and the top level assembly, whereas HMT was in charge of the damping loop and high voltage block design. The overall project is supervised by Thales, the Topic Manager.
Figure 1 shows the work packages organization of the project.
The work is divided within 5 work packages:
WP1 concerns the specification and the characterisation strategy of the ASIC. The goal of this WP is to establish detailed design specifications of each block constituting the ASIC. This WP is very important to enable a smooth execution of the ASIC design (WP2).
WP2 deals with the design of the ASIC starting from the specifications and ending with the layout and the characterisation plan of the ASIC ready for integration. It consists in the design and simulation of each blocks constituting the ASIC, the system design and simulation to assemble the different blocks into a coherent ASIC, and finally the realization of the layout of the ASIC.
WP3 concerns the characterization of the ASIC at laboratory level according to a pre-established characterization plan. For this purpose, a dedicated PCB is designed and realized during the integration of the ASIC.
WP4 deals with the activities concerning dissemination and exploitation of research results produced within this project, attempting to maximize the knowledge transmitted from this research project to the scientific and the industrial world working on aeronautics.
WP5 contains the management activities, including administrative tasks and reporting, but most importantly ensuring the correct planning and execution of the project to achieve the technical objectives within the set deadlines and budget.
Project Results:
This section describes the main scientific and technical results of the ResAcc project. The goal of the project was the design of the ResAcc ASIC to interface the resonant MEMS developed by Thales.
Global architecture
The architecture of the chip is based on user requirements provided by Thales, which also includes different peripheral blocks. It is important to note that the ResAcc ASIC designed in the ResAcc project framework integrates only a part of the complete system that is targeted by Thales. Figure 2 shows a block schematic of the MEMS, the ResAcc ASIC to be designed (in grey), and additional blocks (in orange). The blocks to be integrated on the ASIC are considered as the most critical ones. The other blocks will be external components within the ResAcc project, but will be integrated on chip beyond the ResAcc project to lead to a sensor interface with a minimal count of external components.
The MEMs is composed of 2 resonators, which resonant frequencies are a function of the force transmitted to them by a seismic mass. The principle consists first of sensing the capacitance change of the resonators and amplifying it to a suitable voltage. This voltage is then used for 3 purposes:
• it is fed back through an analog loop to excite the resonator with a suitable amplitude.
• it enters a trigger detection block to enable on-chip digitalization of the acceleration based on a counting scheme.
• it can be digitized by an off-chip ADC for further processing to enable a more precise computation of the acceleration.
The electronics + the resonator are basically an oscillator locked to the resonant frequency of the MEMS resonator. Input acceleration modifies the resonant frequency and also the oscillator frequency. The oscillator frequency is then to be converted into digital information through counting techniques or more sophisticated signal processing algorithms.
The C/V converter is composed of a transimpedance amplifier. The output of the transimpedance amplifier is amplified and fed to the amplitude control loop, an analog buffer to output the analog signal on pads, and a trigger to digitize the analog signal by detecting its zero-crossings.
The amplitude control block extracts the signal amplitude after amplification and full-wave rectification and compares it to a voltage reference. The difference between the sensed amplitude and target is integrated to control the variable gain of the driver.
A damping block provides active electrostatic damping of the seismic mass through sense and drive electrodes.
Acceleration computation principle
The difference in frequency of the two resonators can be measured very easily by counting the number of periods of each resonator during a given time window and taking the difference between the counts. However, as resonant accelerometers have a sensitivity of a few 10s of Hz per g, this approach necessitates very long time windows to reach a high resolution.
It is not sufficient to use zero-crossings to achieve the desired resolution of 0.2mg at the signal bandwidth of 5kHz. Here a different technique is employed. The whole waveform of the resonator is digitised and the frequency shift measurement is performed in the digital domain with a resolution far lower than a full oscillation cycle.
The aim of the project is to develop a sensor interface performing on-chip digitization of the acceleration for low bandwidth and/or low resolution based on a counting scheme, and enabling off-chip computation of the acceleration based on digitalizing the whole waveform when higher performances (bandwidth, resolution) are needed.
Chip layout
Figure 3 shows an image of the layout of the first generation ResAcc ASIC, with the main blocks highlighted. The pad-ring is separated into 2 parts: a digital pad-ring on the left connecting the digital block, and an analog pad-ring on the right. The chip area is 9.3 mm2.
Characterisation set-up
To characterize the ResAcc ASIC, a PCB was developed, which main components are the ResAcc ASIC, the Thales MEMS and a microcontroller to handle data transfer between a PC and the ResAcc ASIC.
Figure 4 shows a picture of the PCB front-side with the ResAcc ASIC position highlighted by a red circle. The PCB holds sockets for the MEMS cell and the ResAcc ASIC to enable easy exchange of these components. Figure 5 shows the PCB backside with the socket to hold the Thales cell highlighted by a red circle. An NXP microcontroller is embedded on the PCB, managing reset sequence, clock generation and the SPI interface with the ResAcc chip. Dedicated firmware for the microcontroler have been developed and validated, allowing high speed SPI exchange. A Python graphical user interface has been developed to enable communication between a PC and the ResAcc ASIC. The graphical user interface enables to control all the registers of the ResAcc ASIC.
Results
The following section provides summary results from the characterisation of the first generation ResAcc ASIC. The ASIC demonstrated satisfactory functional, noise and temperature stability performance and also served as a proof of concept for the system including the MEMS. The full results are reported in the characterisation report.
Issues
Problems with the first generation ResAcc ASIC are observed due to:
• capacitive coupling due to packaging parasitics,
• function of the amplitude control loop
• slow startup behaviour
• gain mismatch between design and measurement in the main oscillators
• gain mismatch between design and measurement in the damping loop
• frequency offset of the damping loop filter transfer function
Power consumption
The power consumption with a 3.3 V supply voltage is slightly below 40 mW.
Main oscillator loop
The transfer function of the main oscillator loop is illustrated in Figure 6 for different value of Vgate, the voltage which controls the attenuation of signal EXC. At low attenuation (Vgate close to 0 V), the transfer function is quite flat up to the cut-off frequency. When the attenuation increases, a peak appears in the transfer function around 400 kHz. This peak is caused by parasitic couplings between the highly sensitive input of the transimpedance amplifier (pad DET) and the excitation pad (pad EXC). At high attenuation of the transimpedance amplifier output, the oscillator tends to lock on this frequency instead at the nominal resonant frequency of the MEMS around 45 kHz, thus preventing a correct functioning of the system.
Simulations of the transfer functions taking into account the injection network, and estimated parasitic couplings between pads internally to the ASIC as well as external couplings and parasitics have been performed. These have shown that the behaviour is related to external package and PCB parasitics and is expected to be corrected with the revised packaging of the second generation.
Figur 7 shows the transfer function of the main oscillator loop for 3 different temperatures (-40 °C, 25 °C and 85 °C) and 3 different gain settings of the transimpedance amplifier. The open loop gain drops by about 10 dB when the temperature increases from – 40 °C to 85 °C.
Damping loop
Figure 8 demonstrates the transfer function of the damping loop for different gain configurations, as measured by Thales. The centre frequency is lower than designed, and the absolute gain is also lower than targeted for the application. These effects are still under investigation.
Charge pump
Figure 9 shows the performance of the integrated charge-pump and regulator and their sensitivity to the pumping clock frequency (MCLK), where the nominal clock frequency is 40MHz. The target voltage and output regulation of the regulator at low loads meet the specification and match with the simulations.
The knee-point (eg. blue, nominal curve at 30µA) shows the point where the internal regulator no longer has sufficient head-room from the charge-pump to regulate correctly.
Startup
Figure 10 shows the start-up of the oscillator. Signal Vgate is maintained at 2 V during 20 s to ensure that the system (MEMS + ASIC) completely stopped oscillating. Then, Vgate is set to 0 V and the time necessary to obtain an oscillation amplitude of 100 mV is measured. Start-up time depends mainly on the setting of the transimpedance amplifier gain, varying between 2.5 s and nearly 13 s. Start-up time is much longer than what was specified (0.5 s). This is due to an insufficient gain of the transimpedance amplifier. In the second version of the ASIC, the gain of the transimpedance amplifier has been increased by a factor 9.
System proof of concept
Figure 11 shows the waveform measured on pads EXC1 and OSCP1 in closed loop (including the MEMS sensor) with an external control of the oscillation amplitude. The frequency is 44541 Hz.
Figure 12 shows the waveform on pads EXC1 and OSCP1 with internal control of the amplitude, obtained by averaging to filter some instability of the Vgate voltage.
Figure 13 shows the signals on pad EXC and OSCP as well as the Vgate voltages for the 2 oscillators of a same chip, without any averaging. The disphony between the 2 channels is -38 dB.
Project continuation
A second generation of the ResAcc ASIC is in development which is expected to correct the observed issues. Although foreseen within the scope of the ResAcc project, part of the development and all of the characterisation of this second generation will be conducted following the project. The positive results of the first generation, especially with respect to the major concerns of noise and temperature stability, give confidence in achieving the design goals with the second generation.
Potential Impact:
The ResAcc project has delivered an integrated sensor interface for a resonant MEMS. The first version of the ASIC exhibits several problems. However they have been identified and corrected on the second version, which will provide a basis to develop an industrial version offering inertial grade performances. This enables miniaturization, power consumption reduction and cost reduction of these accelerometers, which will allow for the widespread use of these products throughout the avionics field.
The continuation of the development of a product ASIC following the characterisation of the second ResAcc generation is planned between the ResAcc project partners and the Topic Manager.
This product ASIC will incorporate further auxiliary functions, including power management, a quartz oscillator and a temperature sensor with ADC, EEPROM and a revised digital functionality.
HMT and CSEM are employing the low-noise design techniques developed in this 0.35µm process in a number of unrelated and non-conflicting projects, primarily also in the sensor domains.
Beyond ResAcc, a variety of technical fields and market segments can be addressed by the project results and the know-how generated by the project. Indirect re-use of the project results can be considered with new projects for CSEM’s Swiss and industrial customers in fields such as:
• The construction segment, where accelerometer based sensor interfaces can be deployed to monitor structural health of the large buildings, bridges, tunnels, etc.
• The automotive field, where sensors and interfaces are taking increasingly larger roles for the driver and passenger safety and comfort.
• The machine industry where miniaturized sensors and sensor interfaces allow efficient monitoring and maintenance.
• The sports/wellness and medical/health segment, where accelerometer based sensor interfaces enable novel products for monitoring the motions of persons for real-time monitoring systems.
List of Websites:
www.resacc-project.eu
Pierre-François Rüedi, CSEM S.A. rue Jaquet-Droz 1, 2002 Neuchâtel Switzerland
