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ASIC 0.5 micron CMOS

Objective

The project aimed to develop Europe's capability in advanced ASIC CMOS processes. Sub-micron CMOS technologies were to be developed, demonstrated and qualified at the 0.7 micron (after 2 years) and 0.5 micron (after 4 years) levels. The reduction in dimensions was to be optimised to achieve very high packing density as well as very high speed for digital custom chips. Packing density targets were about 5000 logic gates/mm{2} in 0.7 micron CMOS and over 7000 in 0.5 micron CMOS.
The ACCES project provided European systems and information technology (IT) users with a multiple sourced, submicron complementary metal oxide semiconductor (CMOS) process offering high packing densities and high speeds. The processes produced are state of the art CMOS application specific integrated circuit (ASIC) technologies at 0.7 micron dimensions.

Following a demonstration at research scale of the 0.7 micron CMOS process, the process flow was installed in the various industrial sites.

The optimization of the 0.7 micron development is ongoing.
A prototyping status was achieved for every technology involved in the planned 0.7 micron process supporting the common design rules. These were demonstrated and are now available for exploitation. Commonality has been employed in the design rules, which should enable easy second sourcing of the technology. Several demonstrators were designed by the users in the consortium, including:
general purpose digital systolic neural network chip;
high density video codec;
ultra high speed asynchronous transmission (ATM) switch component for use in broadband integrated services digital network (ISDN);
composite array.
Due to the work and the involvement of the research centres, the project has also delivered very advanced results for further incorporation in the 0.5 micron technology.
The ACCES project provided European systems and IT users with a multiple-sourced, sub-micron CMOS process offering high packing densities and high speeds. The processes produced are state-of-the-art CMOS ASIC technologies at 0.7 micron dimensions.

The partners in the consortium are proposing common design rules to their potential customers, resulting in a unique multi-sourcing capability. This approach is further enhanced by the specialisation of the partners in various production levels (from short cycle time prototyping through to high volume deliveries) and application areas (industrial, telecommunications, military, etc).

Coordinator

EUROPEAN SILICON STRUCTURES S.A.
Address
Zone Industrielle
13106 Rousset
France

Participants (9)

Alcatel SEL AG
Germany
Address
Lorenzstraße 10
70435 Stuttgart
British Telecom plc (BT)
United Kingdom
Address
81 Newgate Street
EC1A 7AJ London
Centre National d'Études des Télécommunications (CNET)
France
Address
98 Chemin Du Vieux Chêne
38243 Meyland
GEC Plessey Semiconductors plc
United Kingdom
Address
Caswell
NN12 8EQ Towcester
Interuniversitair Mikroelektronica Centrum
Belgium
Address
Kapeldreef 75
3030 Heverlee
MATRA-MHS
France
Address
3008 Route De Gachet
44087 Nantes
MIETEC
Belgium
Address
Westerring, 15
9700 Oudenaarde
STC Components
United Kingdom
Address
15 Maidstone Road
DA14 5HT Sidcup
TELEFONICA
Spain
Address
C\lerida 43
28020 Madrid