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Contenido archivado el 2024-04-16

Integrated Design and Production System

Objetivo

IDPS aims to provide the industry with a state-of-the-art ASIC facility, including a common library, several design systems and a choice of five foundry services.
Integrated design programming system (IDPS) gathers five European application specific integrated circuit (ASIC) suppliers and three system houses to define an advanced ASIC service, based on common concepts, libraries and design methodologies. Using the IDPS approach will give European customers the opportunity to do portable designs, manufacturable by any of the five IDPS vendors. IDPS design methodology is based on a top down approach, using very high speed computer hardware description language (VHDL) and synthesis tools. IDPS digital library is structured in three levels: SystemLib, MacroLib and CoreLib and completed by a family of regular array generators. The only technology dependent parts of the Library are CoreLib and Generator Leaf cells (primitives). These parts will be optimised to each vendor's process for the best performance compromise. This paper presents the main concepts which form the backbone of IDPS, in the field of standards, library structure, generator concepts, process issues and design methodology.
Following the completion of the first or definition phase of IDPS (projects 2270 and 2426), the second phase has now been completed.

Phases 2 and 3 of the project focus on sub-micron processes with 0.7/0.8 micron feature sizes which were available in time for commercial exploitation of the first IDPS results in the second half of 1992.

The key objectives set at the start of IDPS were:

- standardisation, leading to a European industry standard
- a "Common Library", recognised as a European multi-source library
- implementation of the library in the 0.7/0.8 micron processes
- several CAD systems capable of reliable, error-free design of high complexity (1 - 2 million transistor) ASICs
- to ensure semi-second sourcing of circuits designed with the common library, and full second sourcing between groups of the vendor partners (subject to business agreements).
- short turnaround time to prototypes and "right-first-time" designs and prototypes.

Demonstration and Exploitation

The practical usefulness of the library, CAD and prototyping services will be shown by the IDPS demonstrators and test chips. User partners are orienting their demonstrators to products in their application areas. The vendor partners have shown examples of early exploitation of the results. In addition the vendors demonstrated netlist compatibility by each designing (ie, lay-out implementation and simulation) the same representative ASIC circuit example.

The complexity of ASICs has increased during the period of the IDPS project. The IDPS library and tools themselves allow the development of ASICs with a complexity of 1 to 2 million transistors. The design of a demonstrator of this complexity has started in year 3. Exploitation of IDPS results in the 0.7/0.8 micron process started in the second half of 1992, and improvements in turnaround time have been reported.

Exploitation has been demonstrated in 1993 by all partners. ES2 has accepted the responsibility to make the results available to small-volume ASIC customers. Other vendors will concentrate on internal use and larger customers.

Ámbito científico (EuroSciVoc)

CORDIS clasifica los proyectos con EuroSciVoc, una taxonomía plurilingüe de ámbitos científicos, mediante un proceso semiautomático basado en técnicas de procesamiento del lenguaje natural. Véas: El vocabulario científico europeo..

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Coordinador

PHILIPS INTERNATIONAL BV
Aportación de la UE
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Dirección
GERSTWEG, 2
6534 AE NIJMEGEN
Países Bajos

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