The architecture, system software and T9000 transputer hardware for a family of parallel computers based on the interconnect component from the GENESIS project (2702), the T9000 Transputer and the C104 message router chip specified in the PUMA project (2701) are developed within the GPMIMD project.
The aim of the project was to develop an integrated range of high performance parallel computers, and to experiment with demonstrator applications on large configuration of multiple parallel processor (MPP) computer proving the general purpose nature of parallel processing for 10000s of processing elements. Through the work of earlier projects a variety of hardware and software components for parallel computing have been developed and experimental systems have been deployed. Within this project these technologies are drawn together to give rise to a compatible family of European processors, with high performance scientific applications, parallel database transaction servers, and high performance embedded processing. Results include a common programming and architectural framework for high performance parallel computing, UNIX system V4 based parallel machine development, architectural and programming simulations to support next generation parallel computers, and the porting of a number of industrial codes onto large parallel computers.
The fully integrated family of machines will have three classes of nodes:
sparc Viking nodes
200Mflop vector nodes
highly integrated nodes, based on the T9000
The first two nodes have been developed outside this project. Together with the multistage ELITE network developed in GENESIS, they form the basis of the CS-2 machines now being marketed.
For all node types of the family, the common software architecture will deliver:
FORTRAN and C compilers
a parallel programming interface
tools: debugging, performance monitoring, visualisation resource management and administration support advanced concurrent file systems
Special effort is devoted to support real-time programming on T9000 nodes with the development of input/output support hardware and of demonstration applications mounted on the CHORUS real-time kernel developed in the HARMONY project.
Funding Schemeundefined - undefined
BS12 4SD Almondsbury
SO14 3ZH Southampton