Title: Deep Submicron System on Chip (SoC) pilot line demonstration for harsh environment applications in Europe
300mm wafers manufacturing and 65nm technology for space developed by STm, are a worldwide leading item. The European Space Community needs high complexity radiation-hardened reprogrammable FPGAs allowing dynamic partial reconfiguration (DPR) and providing state of the art, tamper proof, security features. These components must be free of export control. A newly available European origin innovative reprogrammable FPGA architecture has been assessed by Atmel and approved by the two main European Primes EADS Astrium and Thales Alenia Space. This technology will be also used for market segment dealing with harsh environment: Avionics, Transport and - Energy. Dynamic partial reconfiguration has been successfully experienced on Xilinx Virtex 4 and 5 families, and tested on Atmel AT280 architecture but where limited by the architecture and tool constraints of existing software. Securing FPGA programming memory has been implemented by Xilinx and Microsemi. Implementation have been broken one way or the other, in particular by RUB, our WP leader for security. Packaging generally used are ceramic hermetic which limits the die size though the overall capability. Organic substrate, silicon interposer should give the solution for high capacity, power dissipation, and high speed signal integrity. Optical links gives the solution to the new challenges of package to package interconnection up to 20GHz. Optical interfaces must be integrated in the package.
The DEMETER project will bring unique innovative solutions by integrating all reprogrammable functions and protection through native code, directly on chip and in software. It will offer European autonomy on space FPGAs, with feature of -55°C to +125°C temperature range a lifetime to be extended to 20 years, hardening at least for atmospheric neutron, high speed IOs and long operating lifetime.
Call for proposal
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Funding SchemeJTI-CP-ENIAC - Joint Technology Initiatives - Collaborative Project (ENIAC)