1.2 Worked performed from the beginning of the project to the end of the period covered by the report and main results achieved so far
The work has been subdivided into seven work packages, including project management (WP1) and dissemination and exploitation (WP2), which are necessary for achieving the ambitious goals of the project. As for the technical work packages, in the first year, the focus was on defining scenarios for the two do-mains considered in this project, namely Smart Home Living (SHL) and Smart Video Surveillance (SVS). Scenarios definition was the output of the following process: i) A review of trending applications/services in the domain of Smart Video Surveillance and Smart Home Living; ii) A collection of scenarios envisioned by the partners in the consortium; iii) A survey of current reconfigurable hardware (FPGA) products and projects. The activities in WP4 focused on extending the OmpSs programming model so that easy programmability could be achieved in embedded systems that include FPGAs and that are made of several boards, as in a small cluster. To do this, the necessary parts of the software stack were developed to properly manage the distribution of code and data at low level through, e.g. appropriate DMA engines and soft-IPs. The mechanisms for implementing data transfers on the FPGA platform have also been evaluated in order to perform the proper selection during the implementation phase. In WP5, the operating system’s re-lated parts were designed and the necessary software interfaces (API) were drafted with the contributions of the interested partners. In WP6, the architecture of an initial prototype of the AXIOM board was de-fined. The first prototypes will be available to the partners during the second quarter of 2016. This initial prototype is based on a 32-bit architecture, which initially seemed to be an interesting entry point for AXI-OM-based systems, although now a more powerful 64-bit architecture is under consideration. A first prototype of the AXIOM-link interconnect has already been demonstrated. In WP7, the initial evaluation plat-form was defined. This evaluation platform is based on both a full-system simulator and on the FPGA development boards. In order to flexibly explore the possible design points, Design Space Exploration tools were developed and made available to the partners. The XSMLL API (a DSM-inspired interface) for managing threads was successfully demonstrated on the simulator. In terms of preliminary results of tests on thread distribution across boards, experiments with an appropriate consistency memory model to overcome classical DSM limitations were presented to the public.
