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REsistive-Switch CompUting bEyond CMOS

Periodic Reporting for period 4 - RESCUE (REsistive-Switch CompUting bEyond CMOS)

Reporting period: 2020-02-01 to 2020-07-31

The age of information relies on the scaling of CMOS technology, which allows the decrease of cost per component, and the improve of computing performance at each technology generation. However, CMOS scaling is slowing down due to inherent physical scaling problems, such as the short channel effects which raise the static power consumption and does not allow the downscaling of the dynamic power consumption. In addition, the transfer of data between the memory and the central processing unit (CPU) introduces a ‘memory wall’ issue, in terms of latency and additional power consumption. All these problems can be solved by novel in-memory computing architectures, which would totally suppress the memory wall and the static power consumption by using non-volatile switches for computing. A novel computer based on this concept would revolutionize the scenario of computing by enabling ultra-high density, ultra-low power logic and analog processors for several applications, from the Internet of Things (IoT), to neuromorphic processors for artificial intelligence.
This project aims at the development and demonstration of a new computer using resistive switch devices for computation and memory within an in-memory computing architecture. The project will address this broad objective from different standpoints, including (i) developing a novel generation of resistive switches with improved window and cycling endurance capability, (ii) develop a novel resistive-switch logic architecture serving as a universal platform for in-memory computing, and (iii) developing novel schemes for analog computing, including brain-inspired neuromorphic computing, by using resistive-switch technology.
Achieving these goals would result in a paradigm shift for the electronic industry and for society, by introducing a scalable technology of devices serving as both switches and memory, thus serving all in-memory applications in both the digital computers and analog systems, such as the neuromorphic networks for object learning and inference. For instance, the availability of non-volatile logic computing schemes will enable low-power microcomputers for the IoT, where event-driven computation takes place only in correspondence of sensory inputs. Massive in-memory computing architectures using digital/analog resistive switches would allow efficient processing of big data problems, such as data clustering and hardware learning accelerators. Analog neuromorphic systems with nanoscaled synapses will enable brain-inspired computation in robots and drones, and allow for low-power, high energy-efficient driverless cars.
During the full duration of the project, the activities have been carried out smoothly and substantially in line with the description of actions. Within the project, the following achievements have been obtained:
1) We have developed a new technology of high performance digital/analog switches, consisting of a stack of Ti electrodes, SiOx dielectric layer, and C bottom electrode. These devices have shown outstanding resistance window (about 1E4 between on and off states), high endurance (above 1E8 cycles) and good retention at high temperature (at least 1 hour at 260°C). Replacing the top electrode with Ag results in volatile devices, with retention in the microsecond range, and on/off ratio exceeding 1E7. These devices are currently being extensively deployed to demonstrate novel resistive logic circuits and neural networks.
2) We have developed a new synapse for spike-timing dependent plasticity (STDP) based on a one-transistor/one-resistor (1T1R) structure. The learning and recognition capability was demonstrated by simulation of a 28x28 neuron network.
3) We have developed a new brain-inspired methodology to perform logic computation within a reconfigurable neural network. This innovative concept outperforms all previous memristive logic schemes by completing all logic operations in just one clock, except for 2 clocks required for the case of XOR and negated XOR. One-bit full adder is completed within 2 clocks and requires just 5 bits, namely the 2 addends, the carry-in, the carry-out and the summation output. This neural network approach is extremely powerful for logic computation.
4) We have designed, fabricated, and tested a new hardware for solving linear algebra problems in one step. The new circuit relies on analogue in-memory architecture with various type of devices, e.g. RRAM or PCM devices to map the coefficient matrix. The circuit is capable of high speed, good scalability and O(1) complexity, which is extremely promising for improving the throughput and energy efficiency of machine learning hardware accelerators.
5) We have designed a new circuit for the solution of regression problems in just one step. The new circuit is organized with in-memory architecture, where data to be processed are directly stored within the crosspoint memory array, which are connected in a feedback loop with operational amplifiers. The circuit is applicable for the training of neural networks in just one step.
These results have been extensively disseminated via international conferences, media coverage, and seminars in the academia and the industry. The high innovation potential of these novel concepts make these findings extremely promising, although it will be not easy to develop marketable products in the near term. The exploitation path is currently being continued in the frame of an ERC-PoC to seek industrialization of some of the new concepts developed in the RESCUE project.
The novel device technology based on SiOx switching shows outstanding performance in terms of resistance window, cycling endurance, and retention. Memory industry already manifested interest in possible exploitation of this technology, given the added value of SiOx being a highly CMOS compatible material, known from decades for its use in the process lines of the microelectronic industry. At first, we plan to encourage the deployment of this novel technology as embedded memory in system-on-chip (SoC) solutions, such as microcontrollers, power chips and IoT hardware. The embedded memory can serve as first niche application for making industries familiar with this technology, and prepare the ground for later, long-term introduction of in-memory computing systems, such as neuromorphic processors or machine learning chips.
The innovative analogue in-memory concept that has been developed is suitable for exploitation in a number of machine learning accelerators, taking advantage of the high energy efficiency and O(1) complexity of computation. We are currently extending this concept to new ideas and new applications in the frame of page rank and other machine learning tools in the cloud. We believe there is significant room for exploration, both at the level of fundamental research in the development of novel in-memory circuits, and at the level of applications in many fields, from smart sensors to data science in the cloud. From this viewpoint, analogue in-memory computing can be one of the contender of the computing accelerator scenario beyond the end of Moore's law.
The holistic approach of the RESCUE project.