First, thorough investigation of the full-duplex current state-of-the art published solutions was performed followed by work of full-duplex transceiver system level and circuit level specifications. The project is based on a new, 28nm FDSOI technology that is not in volume production yet. As a result, the technology parameters change as well as the corresponding design kits. Therefore, researcher put additional effort into automatizing characterization of the 28nm FD SOI technology, generating Matlab code for direct data access for specific biasing points and control parameters. Also, researcher has written Matlab scripts for using that data base for performance optimization and better understanding of trade-offs between technology and system/circuit topology. Researcher has used body biasing technique, available in 28nm UTBB FD-SOI, for fast and efficient change of power and performance characteristics . The main goal was to use this technique to recover the whole design space of the mixer-first receiver in the most robust corners (SSA, SFA, FSA, FFA). New generation receivers, like mixer-first receiver, introduce previously not encountered demands for some circuit blocks. In the traditional receiver architecture base-band amplifier is at the end of the receiver chain and needs to satisfy receiver linearity requirement. However, in mixer-first receiver base-band amplifier is just after down-conversion mixer where due to mixer switches bidirectional behavior it has to satisfy requirements related to receiver impedance matching, noise and linearity. The design goal was to keep approximately same power consumption and the receiver design Figures of Merit (Noise Figure, S11, 3rd order Harmonic Rejection, 5th order Harmonic Rejection, etc.) within +/- 10% range. The paper that presents novel analog optimization methodology that led to significant decrease of the active devices area and tight control of the design parameters will be submitted to IEEE TCAS-II journal. Paper explaining new approach to class AB base-band amplifier design with body biasing, able to significantly reduce circuit area and complexity and recover performance in even the most robust corners, was presented at S3S 2017 conference. Project results related to the body-biasing technique and analog circuits device optimization were presented at 26th International Workshop on Post-Binary ULSI Systems 2017, EWDTS 2017 and ISSE 2018. The new approach to rapid analog and digital integrated systems design was presented during hands-on “Integrated Systems Design” Workshop/ Bootcamp.