Mont-Blanc 3, European scalable and power efficient HPC platform based on low-power embedded technology

Informations projet

Mont-Blanc 3

N° de convention de subvention: 671697

DOI

10.3030/671697

Projet clôturé

Date de signature de la CE 29 Juin 2015

Date de début 1 Octobre 2015

Date de fin 31 Decembre 2018

Financé au titre de

• EXCELLENT SCIENCE - Future and Emerging Technologies (FET)

Coût total

€ 7 968 375,63

Contribution de l’UE

€ 7 968 375,63

Coordonné par

BULL SAS
France

Periodic Reporting for period 2 - Mont-Blanc 3 (Mont-Blanc 3, European scalable and power efficient HPC platformbased on low-power embedded technology)

Période du rapport: 2017-04-01 au 2018-12-31

Résumé du contexte et des objectifs généraux du projet

High Performance Computing (HPC) is a key technology to help tackle many challenges of our century, such as anticipating climate change, or early warnings for extreme weather events. It benefits all citizens. However, with HPC datacenters consuming ever more power, there is a critical need for more energy-efficient solutions.

Back in October 2011, the Mont-Blanc consortium launched the first phase of a project aimed at exploring an energy-efficient alternative to current supercomputers, based on low-power mobile processors, with the ambition of setting future HPC standards for the Exascale era.

Today, energy efficiency is more than ever the primary concern for future Exascale systems, which confirms the relevance of the Mont-Blanc approach. The objective of the third phase of the Mont-Blanc project is to leverage the lessons learned during the first and second phases of the initiative. The project continues to take a holistic approach, encompassing hardware, operating system and tools, and applications, with the following targets:
- Defining the architecture of an Exascale-class compute node based on the ARM architecture, and capable of being manufactured at industrial scale;
- Assessing the available options for maximum compute efficiency;
- Developing the matching software ecosystem to pave the way for market acceptance of ARM solutions.

Travail effectué depuis le début du projet jusqu’à la fin de la période considérée dans le rapport et principaux résultats atteints jusqu’à présent

The main scientific and technological results of the project are the following:

- An industrial prototype (the Dibona platform)
This medium-sized test platform (composed of 16 blades, ie. 48 bi-socket 64-cores compute nodes) made it possible to assess our performance extrapolation with the observation of real applications. It provided a key support to showcase our holistic work and enhance the impact of our project.

- A significant contribution to the Arm HPC software ecosystem
We identified gaps across the entire software stack, and consequently made improvements at all levels, from compilers and scientific libraries, to runtimes and operating systems.

- Application evaluation on Dibona
We structured the evaluation with a bottom-up approach, executing programs with an increasing level of complexity, starting from the simplest micro-benchmarks, going through the most relevant high-performance computing benchmarks LINPACK and HPCG, and finally performing tests with production scientific applications. This showed results in line with state-of-the-art HPC systems

- Performance modeling environment
In the Mont Blanc 3 project, we have pursued the idea of ’multi-scale simulation' where the full simulation workflow consists of various tools to address different abstraction levels of the same simulated system. We have also explored options to reduce simulation time by finding and simulating only a set of representative sections of a particular application. We have demonstrated that these methods can indeed reduce simulation time significantly achieving 10-100x speed up in many cases.

- Design Space Exploration
Leveraging on ’multi-scale simulation' we have performed an exhaustive analysis considering several architectural components relevant for the design of next generation HPC architectures. We investigated hybrid MPI+OpenMP state of the art benchmarks with native input sets. Several conclusions have been extracted from this campaign, which can now be used to drive the design of next generation HPC systems.

Progrès au-delà de l’état des connaissances et impact potentiel prévu (y compris l’impact socio-économique et les conséquences sociétales plus larges du projet jusqu’à présent)

An important aspect of Mont-Blanc 3 was that it aimed to develop home-grown European technologies, and contributed to reinforce the European innovation ecosystem for HPC. This is much needed, as Europe consumes about 29% of HPC resources worldwide, but the EU industry provides only 5% of them (source: EuroHPC JU website)
Indeed, a key outcome of Mont-Blanc is an HPC Arm-powered blade marketed by Atos as part of their BullSequana supercomputer range.

Mont-Blanc is recognized as one of the pathfinder projects that boosted the emergence of Arm-based HPC - now turning into a mainstream technology. During the project duration – from end 2015 to end 2018 - this idea was turned into a reality. We started from a situation with no commercial solution available to reach the point where several key IT players – Atos/Bull, but also Cray, HPE and Fujitsu - propose or are about to propose commercial products.

The impact of the third phase of Mont-Blanc has been widely recognized by the community, with for instance two prestigious HPCwire awards, and twice the honor of the Top500 “Hits and Misses” yearly report ; at SC 2017 we received the HPCwire Editors’ Choice award attributed to the project as ‘Best HPC Collaboration (Academia/Government/Industry)’, and our technological implementation by Atos received Editors' Choice: ‘Top 5 New Products or Technologies to Watch’.

Concerning the software ecosystem, we worked on a mix of open-source and commercial solutions. Whenever possible, open-source contributions have been made. In other cases, our contributions enriched the offering of industrial stakeholders (Arm and Atos).

Mont-Blanc project generic illustration

Dibona prototype

HPCwire award