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Buffer Layer Engineering in Semiconductors

Objective

The major objectives are to:

- Develop techniques for growing good III-V buffer layers on III-V and silicon substrates. The top surface of such layers should be of pre-determined lattice parameter and should be flat and free from defects.
- Develop an understanding of the mechanisms of defect introduction during MBE-type growth methods.
- Assess the optical and/or electronic effect of defects which prove difficult or impossible to eliminate.
- Develop design rules to help guide those who need to grow buffer layers in the future.
Design rules are being developed for the controlled growth of buffer layers on gallium arsenic, indium phosphorus aand silicon substrates. Buffer layers should provide the selected lattice parameter and a defect density no greater than normally available in conventional substrates.

Buffer layer relaxation has been studied for indium gallium arsenic on gallium arsenic for a range of indium content up to 50%. All layers follow the same strain relaxation behaviour, following an empirical curve with a threshold then a steady reduction in residual strain. This appears to hold for material grown by molecular beam epitaxy (MBE), atomic layer molecular beam epitaxy (ALMBE) and chemical beam epitaxy (CBE), as long as 2-dimensional growth conditions can be maintained. Layers under tensile strain may crack and do not follow the empirical curve even after annealing. Considerable progress has been made by the consortium in the rational design of multilayers involving strain steps with and without tensile components such that relaxation occurs at predictable interfaces. The fundamental basis of the empirical curve is being investigated.
APPROACH AND METHODS

It is clear that in the field of III-V devices buffer layers are necessary and are of crucial importance to the controlled manufacture of devices. However, there is little understanding of what makes a good buffer layer. BLES is proposing to make a systematic study in order to gain a complete understanding of the way in which defects are incorporated into growing buffer layers, and of the effect which specific defects then have on electronic or optical performance. This three-way correspondence between growth, characterisation and performance requires more detailed and systematic study than most industrial laboratories are able to mount.

The novelty of the approach is that, firstly, BLES intends to avoid generating threading dislocations rather than trying to filter them out, and secondly, that the designs will actively prevent damage from propagating downwards in a structure. A variety of relaxed and partially-relaxed buffer layers will be grown by MBE, ALMBE and CBE in order to test the universality of an empirical law of strain relaxation over a wide range of compositions and strains. It is hoped that the results will enable the specification of design rules for buffer layers that are applicable to many growth methods and materials. The systems to be studied in most detail are InGaAs/GaAs, InGaAsP/GaAs, InGaAs/InP and GaAs/Si.

POTENTIAL

It is clear that there is considerable potential for the design of layers with controlled concentrations of threading dislocations suitable for subsequent device growth.

Coordinator

THE UNIVERSITY OF LIVERPOOL
Address
Oxford Street
L69 7ZE Liverpool
United Kingdom

Participants (4)

CENTRO NACIONAL DE MICROELECTRONICA
Spain
Address
Serrano, 144
28006 Madrid
OPTRONICS IRELAND
Ireland
Address
C/o Eolas
Dublin
UNIVERSITAT POLITECNICA DE MADRID
Spain
Address
Campus De Montegancedo
28660 Madrid
UNIVERSITY OF CADIZ
Spain
Address
C/ancha, 16
11001 Cadiz