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NEUral computing aRchitectures in Advanced Monolithic 3D-VLSI nano-technologies

Periodic Reporting for period 2 - NeuRAM3 (NEUral computing aRchitectures in Advanced Monolithic 3D-VLSI nano-technologies)

Período documentado: 2017-07-01 hasta 2019-06-30

Segmented Bus (Global Synape) chip by imec
ECG anomaly Detection by use of Reservoir Computing
Demonstration of plasticity effects by CNR on UZH circuit
CSIC designed chip for validation at array level
Layout and characteristics of the 28nm FDSOI multicore spiking circuit
Spirit chip for handwritten digit recognition by CEA
Integration Flow for the 3D+ RRAM technology
Packaged Dynap-Sel circuit
ReASOn chip from UZH to validate plasticity using RRAM
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