Si on SiC for the Harsh Environment of Space

Project Information

SaSHa

Grant agreement ID: 687361

DOI

10.3030/687361

Project closed

EC signature date 18 November 2015

Start date 1 February 2016

End date 31 January 2018

Funded under

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies – Space

Total cost

€ 997 130,00

EU contribution

€ 997 130,00

Coordinated by

UNIVERSITY OF WARWICK
United Kingdom

Periodic Reporting for period 1 - SaSHa (Si on SiC for the Harsh Environment of Space)

Reporting period: 2016-02-01 to 2018-01-31

Summary of the context and overall objectives of the project

Current and future space applications that can benefit from improved power solutions include ion propulsion technologies, used for drag compensation in ESA’s GOCE Satellite and in delivering the BepiColombo spacecraft to Mercury. Furthermore, a drive for high voltage distribution to reduce cable weight in numerous satellite and explorer applications will be enabled by high voltage electronics. However, the challenge of space is one of reliability and efficiency in extreme conditions, where both high and low temperatures are present as well as severe background radiation, that can slowly deteriorate, or even instantly destroy critical devices.

The SaSHa project is focussed on accelerating the development of an entirely new generation of power electronics semiconductors devices benefitting both space and several terrestrial applications. Exploiting the high voltage and high temperature properties of SiC, and the electrical performance of Si and silicon-on-insulator technologies, the resulting power devices will be especially equipped to cope with the harsh environment of space. Proof of concept prototype power devices (diodes, lateral MOSFETs and lateral IGBTs) will be developed that incorporate a novel Si-on-SiC (Si/SiC) substrate solution into state-of-the-art device architectures. The resulting power devices will be capable of working at voltage ratings from 50 to 600 V, in extreme radiation conditions and at temperatures up to 300°C, characteristics unavailable in the current power market, let alone for space.

The objectives of the project are as follows:
O1. To develop an advanced TCAD-based model of the Si on SiC device technology to define the optimal layout and design of the new radiation hard Si/SiC transistors.
O2. To develop high quality, device-ready Si-on-SiC substrates.
O3. To develop the first Si/SiC power electronic transistors capable of operating in the harsh environment of space
O4. To demonstrate device robustness in under extreme temperature and radiation conditions.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

The SaSHa Project: A list of achievements:

WP2. Simulation.
• First of a kind Si/SiC power MOSFET and IGBT devices have been designed and optimised using simulations and newly developed TCAD models for Si on SiC bonded substrates. This was refined using the feedback from the first MOSFET process and test devices. Their proof of concept and a publication detailing their full characteristics will be forthcoming in 2018.
• One of the key objectives was to develop an immunity to single event effects up to a very challenging LET of 90 MeV. The device design realised by the project team involved a novel device structure with p-type shorts surrounding the n-channel, such that in the event of a heavy ion strike, the charge accumulated could be efficiently dissipated, avoiding latch up and permanent device destruction. This work was the subject of conference publication.

WP3. Materials.
• A novel radical activated Si-to-SiC wafer-bonding process was developed. Anneals performed to produce a permanent bond are performed at low-temperature, meaning that little strain is induced into the interface, reducing the density of interface charge. The final wafers produced by this method with material from a second SOI supplier proved the material to be of excellent quality, free of doping issues that were present earlier in the project. This has resulted in a patent, with publications to follow in 2018.
• The Si/SiC process is now scalable for future production.

WP4. Fabrication.
• A distinct challenge of this project was learning how to process the Si/SiC material for the first time. In particular, the combination of the unique material and the analysis of the Si device layer, which flipped from n-type to p-type, was the feature of an invited journal publication in the Materials Science in Semiconductor Processing journal.
• A Si/SiC LDMOSFET and LIGBT process was established. In each of the development cycles, this would have produced successfully working devices, but for the materials problems. As such, with a significant breakthrough in the Si/SiC material development having occured at the end of the project, these devices will be produced in 2018, with further publications to follow.

WP5. Reliability.
• Introduction of NO2 treatment into thick field oxide fabrication process provided very encouraging results in terms of radiation hardness. Radiation induced oxide charge values were extracted to be lower than values included in TCAD simulations to assure invariance of breakdown voltage under TID effect.
• First SEB tests on second generation devices were encouraging, revealing a device successfully operated at Vd=390 V under Xe ions (LET=62.5 MeV/cm2/s). This suggests that Si/SiC LDMOS devices merit further studies for rad-hard applications.

WP6. Dissemination
• In the second six months, a promotional video was produced and launched on the website, introducing the project and the concepts involved.
• Academic output from the project currently stands at one invited journal paper, two other journal publications and 6 conference publications, involving talks at ESA’s European Space Power Conference (ESPC), the European Silicon Carbide Conference (ECSCRM), Solid State Materials and Devices (SSDM) and High Temperature Electronics Network (HiTEN).
• The most significant results and papers are still to come, and several more conference and journal papers acknowledging the SaSHa project will be published in 2018 and 2019.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

Progress beyond the state of the art:
• A patented 100mm Si-on SiC wafer-bonding process has been developed using a novel low-temperature process such that little strain is induced into the interface. This material is beyond the state of the art in SOI wafers, offering the prospect of lateral silicon devices being developed that can better handle self-generated heat. The final iteration of the process, proven to be free of substantial charge at the interface, which in the past skewed device performance.

• A first of a kind MOSFET and IGBT design has been developed to exploit the Si/SiC's unique propertiesd. Designed for space, they are shown in simulation to withstand a single event upsets up to a very high level (LET = 90 MeV/cm2/s while fully reverse biased at 600 V).

• Fabrication trials produced a first generation of working Si/SiC MOSFETs and IGBTs. Early materials issues prevented their development to 600 V, but they showed good performance in radiation testing, revealing a device successfully operated at Vd=390 V under Xe ions (LET=62.5 MeV/cm2/s).

Beyond SaSHa – 2018-2019: Progress on these wafers continues beyond the end of the SaSHa project. With beyond-state-of-the-art Si/SiC having been developed at the end of the project, the device development continues such that 600V devices will be developed and tested in 2018. These will be a first-of-a-kind, and as such will be tested and benchmarked to the same devices in SOI, at tempertaures up to 300oC and in a high radiation environment.

This work continues towards new power device solutions, for the current and future space applications originally targeted including ion propulsion technologies, high voltage distribution and for smaller, lighter on-board power supplies.

Image of a 100mm Si-on SiC wafer.