CORDIS provides links to public deliverables and publications of HORIZON projects.
Links to deliverables and publications from FP7 projects, as well as links to some specific result types such as dataset and software, are dynamically retrieved from OpenAIRE .
Deliverables
The fabrication of a range of simple test device structures (no more than three photolithographic steps) to better understand the Si/SiC thin film materials characteristics, prior to full transistor fabrication. Devices to include lateral power Schottky PiN and gated diodes, MOS capacitors, resistor bars, TLM structures and hall bars. Equivalent devices on SOI and Si will benchmark performance. All material will come from WP3, the mask set and procedure from WP2.
Delivery of Si/SiC LDMOS and LIGBT die for reliability and radiation testing in WP4 (opens in new window)The fabrication of Si/SiC LD-MOS and LIGBT rated at 200 and 600 V. Fabrication of each device will be a long process requiring several photolithography steps to define areas for metal deposition, oxidation, implantation and etching. It is expected the process will have to be optimised and is therefore likely to be iterative, with each device produced improving upin the last.
Delivery of SOI for processing trials in WP3 (opens in new window)Defining, sourcing and purchasing appropriate materials for Si/SiC formation, and for benchmark SOI and Bulk Si devices. 4-inch 6H-SiC and SOI wafers will be purchased from Norstel and Icemostech, respectively, for the tasks of this WP.
Delivery of final Si/SiC material for test device structures. Communication of interim physical characterisation informing WP3 (opens in new window)Development of Si/SiC bonding trials, refining historic TNI-UoW trials for 100mm and 150mm wafer coverage. This task will involve SiC-to-Si wafer bonding (WB) process development and optimization of bonding parameters including radical activation using remote plasma for the purpose of transferring a thin Si film onto a SiC wafer. The wafers will be bonded under vacuum (10–5 mbar) and exposed to free radicals generated by a remote plasma ring prior to wafer-to-wafer contact. Wafers will then be bonded under a force while being annealed in-situ. Post bonding Si wafer to SiC wafer, Si substrate will be thinned down to a couple of microns. In case of using SOI, the whole Si substrate will be removed. In either case, the substrate thinning will start with grinding followed by chemical etching. The greatest challenge here will be the bond strength which should tolerate the mechanical stress during mechanical grinding/polishing. Results obtained at this stage will be fed to Task 3.2 for bonding process modification accordingly to increase the bond strength. Depending on the bond strength (go/no go decision making point), we may develop annealing step, micro-channel formation and/or use an ultrathin interfacial layer to enhance the bond strength. Following this step AFM measurement will be used to define the roughness of the Si film transferred onto SiC wafer after polishing. In the case of SOI wafers, the oxide layer will be removed chemically after grinding the Si substrate.
Delivery of initial Si/SiC material for test device structures. Communication of physical properties informing WP3 (opens in new window)Development of Si/SiC bonding trials, refining historic TNI-UoW trials for 100mm and 150mm wafer coverage. This task will involve SiC-to-Si wafer bonding (WB) process development and optimization of bonding parameters including radical activation using remote plasma for the purpose of transferring a thin Si film onto a SiC wafer. The wafers will be bonded under vacuum (10–5 mbar) and exposed to free radicals generated by a remote plasma ring prior to wafer-to-wafer contact. Wafers will then be bonded under a force while being annealed in-situ. Post bonding Si wafer to SiC wafer, Si substrate will be thinned down to a couple of microns. In case of using SOI, the whole Si substrate will be removed. In either case, the substrate thinning will start with grinding followed by chemical etching. The greatest challenge here will be the bond strength which should tolerate the mechanical stress during mechanical grinding/polishing. Results obtained at this stage will be fed to Task 3.2 for bonding process modification accordingly to increase the bond strength. Depending on the bond strength (go/no go decision making point), we may develop annealing step, micro-channel formation and/or use an ultrathin interfacial layer to enhance the bond strength. Following this step AFM measurement will be used to define the roughness of the Si film transferred onto SiC wafer after polishing. In the case of SOI wafers, the oxide layer will be removed chemically after grinding the Si substrate.
Publications
Author(s):
Chunwa Chan, Philip A. Mawby, Peter M. Gammon
Published in:
IEEE Transactions on Electron Devices, Issue 63/6, 2016, Page(s) 2442-2448, ISSN 0018-9383
Publisher:
Institute of Electrical and Electronics Engineers
DOI:
10.1109/TED.2016.2550865
Author(s):
C. W. Chan, F. Li, A. Sanchez, P. A. Mawby, P. M. Gammon
Published in:
IEEE Transactions on Electron Devices, Issue 64/9, 2017, Page(s) 3713-3718, ISSN 0018-9383
Publisher:
Institute of Electrical and Electronics Engineers
DOI:
10.1109/TED.2017.2719898
Author(s):
Peter M. Gammon, Fan Li, C.W. Chan, Ana M. Sanchez, Steven A. Hindmarsh, Farzan Gity, Tanya Trajkovic, Valeriya Kilchytska, Vasantha Pathirana, Gianluca Camuso, Khaled Ben Ali, Denis Flandre, Philip A. Mawby, Julian W. Gardner
Published in:
Materials Science Forum, Issue 897, 2017, Page(s) 747-750, ISSN 1662-9752
Publisher:
TTP ltd
DOI:
10.4028/www.scientific.net/MSF.897.747
Author(s):
P.M. Gammon, C.W. Chan, F. Gity, T. Trajkovic, V. Kilchytska, L. Fan, V. Pathirana, G. Camuso, K. Ben Ali, D. Flandre, P.A. Mawby, J.W. Gardner
Published in:
E3S Web of Conferences, Issue 16, 2017, Page(s) 12003, ISSN 2267-1242
Publisher:
EDP Sciences
DOI:
10.1051/e3sconf/20171612003
Author(s):
C.W. Chan, Fan Li, Philip A. Mawby, Peter M. Gammon
Published in:
Materials Science Forum, Issue 897, 2017, Page(s) 751-754, ISSN 1662-9752
Publisher:
TTP ltd
DOI:
10.4028/www.scientific.net/MSF.897.751
Author(s):
P.M. Gammon, C.W. Chan, F. Li, F. Gity, T. Trajkovic, V. Pathirana, D. Flandre, V. Kilchytska
Published in:
Materials Science in Semiconductor Processing, Issue 78, 2018, Page(s) 69-74, ISSN 1369-8001
Publisher:
Pergamon Press
DOI:
10.1016/j.mssp.2017.10.020
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