Livrables
Updated version of D1.2 at M24
Margining ReportLinked to T5.4. This is a document that will define a series of stability criteria for the FB-DRAM based memory. Extensive high sigma Monte Carlo simulations will be ran to validate these stability criteria in order to demonstrate design robustness and high yield. The simulations will be run across extremes of voltage and temperature as defined by the design specification. The Margining Report, in conjunction with the Silicon Evaluation Report will provide potential customers with a high degree of confidence in the product.
List of networking activities to promote REMINDER researchLinked to T6.5. This deliverable will collect, at the end of the project, a list of the activities performed for the the networking and collaboration with other European initiatives to contribute to the creation of the European Research Area (ERA).
Characterization of optimized FB-DRAMs fabricated in the first run of WP1 in FD28This deliverable is linked to task T2.4, whose main goal is the selection and definition of the optimized memory cell to be developed by REMINDER taking as starting point the devices fabricated in run 1. The selected memory cell will be used as input in Run 2. The deliverable will contain the results on the full characterization of all the variants/candidates fabricated in run1, the comparison of the experimental results and the simulations made in WP3, the specifications in terms of material composition, thickness, channel lenght, doping, gate oxide, architecture of the S/D regions, etc., of the selected memory cell.
First REMINDER Industrial workshopLinked to T6.3, Exploitation plan. This deliverable will report on the outcome of the first industrial workshop organized with industrial companies contacted during Task 5.1 and 5.2 to obtain a feedback from potentially interested partners and to start discussions on the exploitation of the results. It will contain a booklet with the communications presented in the workshop.
First year technical reportLinked to T6.1. This deliverable will report on the activities developed and the outcomes achieved during the first year of the project.
Characterization of optimized FB-DRAM for sub-14nm technological nodesThe deliverable is linked to task T2.8. It will contain the results about the characterization of advanced memory cells based on band structure engineering in the Source-Channel-Drain region will be tested according to the developed measurement techniques in T2.1 and T2.4. The fabrication of these devices will be carried out in T1.5 First electrical data will serve to demonstrate the benefit of such architecture and to feed both the simulation WP3 and the compact model development in WP4. These data will serve the TCAD based devices benchmark study which will result from WP3 (T3.6) for ultimate devices architecture. Two versions of these deliverable will be provided: a first one at M24, after the fabrication of advanced memory cells based on Si nanowires and 3D structures during the second year of REMINDER. The outputs of these deliverable will be used to improved the advanced memory cells fabricated during the third year. The characterization results on these memory cells will be collected in an upgraded version of the deliverable available in M36.
Low power DRAM architecture specification and preliminary datasheetThis delieverable is linked to task T2.4. Already In run 1, a first preliminary implementation of a memory block optimized from the point of view of power comsuption will be included. Based on the characterization of this preliminary memory block, and the characterization of the specific memory cells fabricated in run 1, architectural considerations for the complete DRAM block implementation will be evaluated. In particular those that support low voltage and low power operation will be prioritized. Specific circuit topologies for decode, sense amplifier, refresh and timing control will be considered. This will culminate in a proposal for an optimal memory block architecture to fully exploit the FB-DRAM cell developed by the REMINDER project. A preliminary datasheet will be prepared in order to engage potential customers and ensure market considerations are catered for. The results and outcomes of these tasks will be collected in this deliverable.
Comparison data to ReRAM and Magnetic memoriesLinked to T5.6. This deliverable will report on the comparison of electrical performance of DRAM with cutting edge ReRAM and Magnetic memory. These comparisons will be based on the available data published or under developing in Lab scale.
CMOS Lot primary characterization (updated version of D1.2 at M42)Updated version of D1.2 at M42 after Run3 fabrication.
CMOS Lot primary characterizationElectrical and structural characterization of the devices fabricated at the three programmed runs. This deliverable will content the results from Task T1.4. This task concerns the characterization of the processed memory devices. The statistical characterization carried out with industrial parametric probers (600 and 680 Keithley) aims to check the conformity of the full CMOS process with embedded 1T-DRAM. Thus the main technological parameters (dielectric thickness, sheet resistance, etc…) and electrical parameters (threshold voltage, current level in various regimes, etc…) are statistically measured on each wafer for all geometries (gate length, channel width, etc…) implemented on the test vehicle. Analyses of these electrical measurements allow controlling the various process steps and The first version of the deliverable will be submitted at M18 after the outcome of the first run. There will be upgraded versions after second run (M24) and after the third run M30. Three sets of memory structures will be fabricated in CMOS FD28 and FD14 technology: Run 1: Fabrication of optimized FB-DRAM solutions (selected after benchmarking of Run 0 devices) and first approach to the memory matrix. Run 2: Results from the first run will educate the memory array design of the second run, which will be limited to the optimized version of the best FB-DRAM variant. In addition, a second set of optimized FBDRAM solutions will be fabricated, taking into account the results of the first run. The devices and structures fabricated in WP1 will be carefully measured in WP2 and simulated in WP3, in order to extract the parameters of the compact models developed in WP4. Run 3: The data will be useful to define end-user applications using the optimized memory solution and to fabricate the memory demonstrator in Run 3.
Evaluation of memory cells from design perspectiveThis Deliverable is related to Task T1.7, and will contain its outcomes: The electrical parameters obtained in Task T1.4 (D1.2) will be reviewed and a preliminary assessment undertaken as to how the characteristics of the various memory cells could affect the overall DRAM design.A first version of the deliverable will be ready at month M19, after the first run. An upgraded version will be elaborated at M28, after the secon run.
Integration and fabrication of FB-DRAM cells using III-V nanowiresThis deliverable is linked to Task T1.6. which concerns the development of process modules for the III-V memory cell fabrication and its integration. This deliverable wil contain the descripstion of all the actions developed to achieve this goal, and the different accomplished outputs: a) Test structures to derive the physical properties of III-V nanowires b) Process modules for III-V nanowire device fabrication c) Integrated III-V nanowire memory cell
Simulation of FB-DRAM variability using DOE and surface response techniquesThis deliverable is linked to T3.4. It will contain the results of the analysis of the influence of the influence that the statistical variations of the technological parameters have on the performance of FB-DRAM cells (retention time, current levels, power consumption, etc.). The variability aspects of memory circuit-design and manufacturability with accurate leakage models will be taken into account. Methods which enable detailed predictions of variability at the circuit-level without sacrificing total simulation time will be developed. Activities will focus on two types of variability simulations: - Die-to-die variations. -Intra-die variations and component mismatch.
Technical specifications of targeted application and benchmark resultsLinked to T5.2. This deliverable will contain the technical specifications for REMINDER FB-DRAMs. These specifications will include the traditional power/performance/area (PPA) figure of merit, but will also emphasize additional parameters like the size of the memory array, the data rate, the allowed voltages, price of the devices, technology constraints…
Advanced physical simulation and optimization of FBDRAM cells using 3DMSEMC tools.Linked to T3.3 and T3.6. Once the 3D-MS-EMC simulator has been implemented, calibrated and fully validated for the simulation of advanced Si-nanowire bsed devices (FinFETs, Tirgates, etc.) as detailed in D3.8, it will used to simulate and optimize FB-DRAM memory cells based on these advanced FET devices. Deliverable D3.11 will collect the results of the simulations performed and the memory cell optimization process.
Development of new simulation tools: Multisubband Monte CarloLinked to T3.3. The deliverable will describe the efforts and activities developed to achieve a Multi-Subband Ensemble Monte Carlo simulator both for electrons and holes in ultrathin SOI devices in transient and stationary conditions. In particular we will focus on: - Development and implementation of new scattering models: (i) impurity scattering and remote phonon scattering for describing high k dielectrics; (ii) confinement of phonons in ultrathin semiconductor layers. - Study of the influence of technological and geometrical parameters on the carrier transport properties in realistic ultrathin FB-DRAM devices. -Benchmarking of the different FB-DRAM cells, structures and materials. Selection of the FB-DRAM cell for pragmatic implementation.
List of dissemination and training actions to promote REMINDER researchLinked to T6.2 List of dissemination and training actions to promote REMINDER research. The results obtained by the consortium will be reported at major European, US, and Far East technical conferences and workshops. The refined papers will be subject of scientific journal articles. To further improve the dissemination level, the consortium will organize two international workshops in FB-DRAMs: the first in the middle of the project (M18) months and the second before the end of the project (M30): the major results achieved by the REMINDER consortium will be presented. Training of young researchers is other main concern of REMINDER consortium. In this sense, and taking advantage of the participation of REMINDER partners in major European Training Networks (such as EUROSOI), lectures on REMINDER research will be scheduled in summer school (MIGAS and nanoKISS) and European doctoral programs of INPG, UGR and GU. All the activities performed by the project will be listed and summarized in this deliverable at the end of the project.
Functional characterization of the memory matrixThis deliverable is linked to Task T2.7. The deliverable will report on the functional characterization of the Integrated memory array (demonstrator). The memory array will be tested with pulse trains according to test algorithm via word line. Through this work, functional error will be detected and completely checked by DRAM tester. At first stage, functional test will be done on wafer probe station and after full package, DRAM will be tested with logic function tester. A first version will be launched at M27 withe results obtained on wafer, and an upgraded version will be elaborated with the results obtained with packed devices at M33.
Development of the simulation methodology for conducting detailed transient analysis and systematic resultsLinked to T3.2. It will contain the simulation methodology and the results for the systematic study of the transient behavior of the different memory cells to reveal dynamic aspects related to programming, reading and retention. Transient TCAD simulations and refined Monte Carlo simulations will be used.
Characterization of failure modes at extremely accelerating conditionsThis deliverable linked to Task T2.5 will collect the results obtained on the failure mode analysis performed on the memory cells and memory blocks fabricated in Run 2 and Run 3. In particular, the failure mode analysis will consist of: -Electrical characterization at higher temperature, electrical overstress, humidity, mechanical vibration, and thermal shock -Physical characterization at higher temperature, overstress, humidity, mechanical vibration, and thermal shock. A first version obtained on Run 2 devices will be launched at M23. This results will be used for improving devices fabricated in Run 3. The results regarding Run3 devices will be contained in the upgraded version of this deliverable will be available at M30.
Fabrication of FB-DRAM memory cells using Si nanowires, and 3D integration.This deliverable is linked to Task T1.5, which is the fabrication of memory cells targeting sub-14nm node. Especially this task will be focused on realistic architectures to address sub-14nm technological nodes: both FDSOI and TriGate architectures will be envisaged in the 14nm FDSOI route. Based on the evaluation of needed advanced process modules in T1.1 and definition of additional advanced process steps, A2RAM architectures will be processes based on a SiGe/Si heterostructure for both WRITE and READ operations. Ease of integration will be preserved in this prospective task aiming to take advantage of band structure engineering to improved major figures of merit at memory cell level. The following key points will be considered: - Architecture identification to address sub-14nm technological nodes with first TCAD evaluation of the benefit of 3D non-planar architecture compared to planar FDSOI (linked to WP3) and advantage of the positive impact of the heterostucture based advanced memory cell; - Advanced Lot processing following the 14FDSOI route and preserving the ease of integration; - First electrical characterization of processed advanced memory cells to address sub-14nm and feedback on TCAD results for TCAD optimization of the integrated architecture (linked WP2 & WP3).
Final reportLinked to T6.1. This deliverable will report on the activities developed and the outcomes achieved during the project.
REMINDER Data Management PlanLinked to T6.2, Scientific dissemination and training. The purpose of the Data Management Plan (DMP) is to support the data management life cycle for all data that will be collected, processed or generated by the project. A DMP is a document outlining how research data will be handled during a research project, and after it is completed.
Preliminary calibration of TCAD simulations based on parameters extracted in WP1 using pre-existing devicesThe deliverable is linked to T3.1 and T3.2, and will collect the calibration results of TCAD simulations by comparing the simulated results with the parameters extracted in WP1 using pre-existing devices. The calibration will include both stationary and transient behaviour of the devices.
Second REMINDER Industrial workshopLinked to T6.3, Exploitation plan. This deliverable will report on the outcome of the second industrial workshop organized with industrial companies contacted during Task 5.1 and 5.2 to obtain a feedback from potentially interested partners and to start discussions on the exploitation of the results. It will contain a booklet with the communications presented in the workshop.
Development of new characterization techniques for the extraction of “transient” parameters and memory performanceThis deliverable is linked to Task T2.2. The goal of the task is to quantify the memory mechanisms is various devices already available at the technological partners of the Consortium. The deliverable will contain the results of the outputs achieved: -Probe the memory effect in various structures: (i) Scaled FD SOI MOSFETs, (ii) Double-gate FinFETs and nanowires. - Measurement of the impact of high temperature operation on the retention time, programming speed, and current margins on the different devices. - Provide inputs, which together with those of T2.3 and WP3, will guide the architecture design of devices to be fabricated in WP1 and models to be developed in WP4. - Validation of simulation results obtained in WP3. - Design of test pattern - Design of test algorithm (testability, system, procedures of failure analysis) - Electrical characteristic analysis (I-V, C-V) - Physical characteristic analysis (Atomic Probe Tomography, SIMS, EXAF, RBS, EELS, Stress/strain analysis)
Calibration of the 3DMSEMC simulator: FinFET, SiNW and FB-DRAM benchmarking.Linked with T3.6. It will describe the activities developed and the results achieved during Implementation and validation of a 3DMS-EMC simulator for the study of next-generation nanowire transistors needed to overcome the problems arising from the aggressive scaling in the design and fabrication of ultimate device and, in particular, FB-DRAM cells. It also contain the benchmarking of future nanodevices using 3DMS-EMC (FinFET, SiNW and FBDRAM).
Characterization of III-V nanowires and devicesThis deliverable is linked to task T2.9, which is the characterization of III-V nanowires and devices fabricated in WP1. The deliverable summarizes the results obtained related to: -III-V nanowire structural and electrical properties -III-V nanowire device and module characterization A first version of this deliverable will be launched at month 12, and upgraded versions will be elaborated at month 24 and month 36.
Implementation of the novel FB-DRAM generic structures in 2D TCAD simulators.Linked with T3.1 & T3.2) Implementation of the novel FB-DRAM generic structures in 2D TCAD simulators. Calibration/validation of the 2D/3D TCAD tools, with the physics parameters extracted in WP2, for simulation of the basic DC characteristics (drain and gate currents, body potential variation, etc.
FB-DRAM optimization for the first fabrication runLinked with T3.1, T3.2 & T3.5: FB-DRAM optimization for the first fabrication run (WP1): determination of the architectures, bias conditions and technological parameters required to achieve best static (current level, power consumption) and dynamic (programming, reading and retention) performances.
FB-DRAM optimization for the second fabrication runLinked with T3.1, T3.2 & T3.5: FB-DRAM optimization for the second fabrication run (WP1): determination of the architectures, bias conditions and technological parameters required to achieve best static (current level, power consumption) and dynamic (programming, reading and retention) performances.
Compact models and assessment of the model accuracy based on comparison of simulation and measurement resultsLinked to T4.2. The deliverable will contain the description of several compact models with different complexity and precision. These models will be obtained from the simplification of the semi-analytical model developed in T4.1 and explained in D4.1
Report on Communication activitiesLinked with T6.4. This deliverable will collect, at the end of the project, a list of the activities performed to communicate the results and research activities developed in the framework of the project to the large, non-expert audience of the society through different actions, whose ultimate goal is to explain why European support for Research is essential and beneficial to the European Society.
Definition of the electrical parameters required by the simulation and modellingThis deliverable is linked to Task T2.1, development of measurement techniques ans setups to determine the key parameters and performance of FB-DRAMs. It will contain the information related to the specific outputs of the task: -Definition of specific test structures based on the definition of all the electrical characteristics needed for model extraction in close interaction with WP4 and WP1. -Extraction of electrical and physics parameters relevant to transient effects in FB-DRAM (lifetime, leakage currents, mobility, series resistance). -Determination of the efficiency of the injection mechanisms for the ‘1’-state programming. -Evaluation of the retention time based on transient measurements. -Measurement of the impact of high temperature operation (> 80°C) on the retention time, programming speed, and current margins. -Development of characterisation procedures to estimate the transient body potential variation by using direct (body contact) and indirect methods.
Extraction of the physics parameters needed in compact models and designThis deliverable is linked to task T2.6, and it is closely related to WP2, WP3 and WP4. The techniques developed in T2.1 will be applied to extract the parameters needed for fine tuning of compact and semi-analytical models. This deliverable will collect the results about: - Carrier lifetime: determined with the measurement setup used for retention time characterization. - Parameters of B2BT, impact ionization and bipolar transistor: temperature behaviour. - Diffusion and depletion lengths: necessary for modelling junction leakage current and retention capability. - Series resistance and carrier mobility: required for modelling the current levels and reading speed. -Short-channel effects: needed to evaluate the limits of scalability Four sets of devices will be considered along the life of the project: run0 - Devices already avaliable run1- First lot fabrication run2- Second lot fabrication run3- Third lot fabrication After each run, the physics parameters will be extracted. Therefore, the deliverable will be updated every six months, after the first version in M12.
Technical requirements for the modelling platformLinked with T4.1: Numerical and analytical modelling of transient body potential, injection mechanisms related to programming, leakage current relevant for the retention time and scaling effects. D4.1 will contain the equations and parameters of the model develop to take into account the dynamic behavior of a FB-DRAM.
Description of the technical requirements for advanced process modules to be included in first runDescription of the technical requirements for advanced process modules to be included in first run
Characterization of the optimized FB-DRAM in the second run of WP1 in FD14This is related to task 2.4. It is an upgraded version of D2.5 but taking as input the results of Run 2 of WP1 in FD14 technology. The outcome of this task is the definition of the optimized memory matrix architecture and memory demonstrator which will be implemented in Run 3.
Spice macro compact model for selected FD_DRAM cell structureLinked to T3.3 and T3.4. The deliverable will describe the Spice macro models which describe the electrostatic behavior of FBDRAM cells designed in REMINDER, based on models developed in T4.1 and T4.2. The macro model development will be first based on a behavioural model in order to establish the topology of the core model and, based on this first step, the physics-based analytical model will be developed in Verilog-A in order to be fully compatible with SPICE simulators. The uniform and statistical compact modelling strategies will be developed for Spice macro model of selected FD_DRAM cell. The Spice macro model will be implemented into the PDK, and it will be improved at every device design iteration stage either in TCAD or in Silicon.
Carrier transport in III-V nanowires: Development of scattering mechanisms and 3DMS-EMC integrationLinked to T3.3 and T3.7. This deliverable will describe the modules necessary to be implemented in the 3DMS-EMC simulator to take into account the scattering mechanisms specific for III-V nanowires.It will also contain the results achieved about the simulation of carrier transport in III-V NWs using advanced simulation tools.
Development of accurate models to describe band structure related effects in III-V nanowires.Linked to T3.7. The deliverable will collect the results obtained on the advanced simulation of III-V nanowires, focusing on the detailed band structure description of III-V NWs including CB-VB interaction and strain.
Second year technical reportLinked to T6.1. This deliverable will report on the activities developed and the outcomes achieved during the second year of the project.
Linked with T5.3. Test chip samples integrating multiple eDRAM instances. Together with the test chip, a detailed silicon evaluation report will be provided.
Linked to T4.3 and T4.4. A toolbox containing building blocks for a library of complex memory matrix array including the simplified models derived in T4.2 and T4.3. Models with variable complexity (temperature effects included) will be considered, from very simple/fast-computing models to advanced/slow-computing models. The models will be checked against measurements (WP2) and numerical simulations (WP3). For selected devices, the models will be checked in simple demonstrators, memory matrix arrays fabricated in WP1. The toolbox is aimed as a true ‘plug and play’ library which has a potential to be applied for all versions of FB-DRAMs. The toolbox will aim to be implemented into SPICE, ELDO, etc. The toolbox will allow the selection of particular FB-DRAM structure (e.g. single gate, double gate, multi-bodies, variable dimensional parameters, etc), operating conditions (e.g. bias, temperature), injection programming method (e.g. tunnelling, ionization, or bipolar), suited transistor model (semi-analytical or compact), and electro-thermal model. Using these models FBDRAM cell dynamics will be evaluated and explored feeding back results so the models may be optimised if necessary in order to ensure modelling accuracy in the commercial design environment.
Complete embeddedLinked with T4.5. Functional designs or memory arrays in order to find applicable solution for the read and write processes, to prove the integration of the RAM concept in a real products and to assess the performance of the memory cell in its environment. It consist of: -Addendum of an existing Process Design Kit (PDK) including the Design Rule Check (DRC) and Layout versus Schematic (LVS) codes compatible with the new devices. -Validation of PDK plus DRC/LVS and parasitic extraction rule decks needed to enable the design process. - Small scale standalone memory arrays conceived to demonstrate the feasibility of the memory integration and to enable silicon proofs of concept -Proof of concept of large-scale memory arrays for embedded applications.
Embedded FB-DRAM memory compilerLinked to T5.5. The deliverable consists on a silicon compiler for low power eDRAM based on the FB-DRAM cell developed and optimized by the REMINDER project.
Linked to T5.1. This deliverable will consist on a catalogue of end-user applications for which FB-DRAMs can potentially become the primary option. Typical applications are graphic processors, servers, multimedia chips for mobile devices and mobile game devices. Evaluation of the various applications specifications in term of power, performance and area requirements will be developed.
Linked to T6.1. Website of REMINDER consortium A project web-site will be set-up with a public area presenting the project objectives, work-plan, partners, main progress, and dissemination plan. A restricted area will also be available to project partners to give access to all documents produced in the course of the project and to provide a dedicated area for sharing scientific documents.
Publications
Auteurs:
Yuan Taur, Joris Lacord, Mukta Singh Parihar, Jing Wan, Sebastien Martinie, Kyunghwa Lee, Maryline Bawedin, Jean-Charles Barbe, Sorin Cristoloveanu
Publié dans:
Solid-State Electronics, Numéro 134, 2017, Page(s) 1-8, ISSN 0038-1101
Éditeur:
Pergamon Press Ltd.
DOI:
10.1016/j.sse.2017.05.004
Auteurs:
L. Donetti, C. Sampedro, F.G. Ruiz, A. Godoy, F. Gamiz
Publié dans:
Solid-State Electronics, Numéro 159, 2019, Page(s) 19-25, ISSN 0038-1101
Éditeur:
Pergamon Press Ltd.
DOI:
10.1016/j.sse.2019.03.044
Auteurs:
C. Navarro, S. Navarro, C. Marquez, J. L. Padilla, P. Galy, F. Gamiz
Publié dans:
IEEE Transactions on Electron Devices, Numéro 66/6, 2019, Page(s) 2513-2519, ISSN 0018-9383
Éditeur:
Institute of Electrical and Electronics Engineers
DOI:
10.1109/ted.2019.2912457
Auteurs:
H.J. Park, M. Bawedin, H.G. Choi, S. Cristoloveanu
Publié dans:
Solid-State Electronics, Numéro 143, 2018, Page(s) 33-40, ISSN 0038-1101
Éditeur:
Pergamon Press Ltd.
DOI:
10.1016/j.sse.2017.12.002
Auteurs:
Santiago Navarro, Carlos Navarro, Carlos Marquez, Hassan El Dirani, Philippe Galy, Maryline Bawedin, Andy Pickering, Sorin Cristoloveanu, Francisco Gamiz
Publié dans:
IEEE Electron Device Letters, Numéro 39/5, 2018, Page(s) 660-663, ISSN 0741-3106
Éditeur:
Institute of Electrical and Electronics Engineers
DOI:
10.1109/led.2018.2819801
Auteurs:
Mukta Singh Parihar, Kyung Hwa Lee, Hyung Jin Park, Joris Lacord, Sébastien Martinie, Jean-Charles Barbé, Yue Xu, Hassan El Dirani, Yuan Taur, Sorin Cristoloveanu, Maryline Bawedin
Publié dans:
Solid-State Electronics, Numéro 143, 2018, Page(s) 41-48, ISSN 0038-1101
Éditeur:
Pergamon Press Ltd.
DOI:
10.1016/j.sse.2017.12.007
Auteurs:
Santiago Navarro, Carlos Navarro, Carlos Marquez, Norberto Salazar, Philippe Galy, Sorin Cristoloveanu, Francisco Gamiz
Publié dans:
IEEE Electron Device Letters, Numéro 40/7, 2019, Page(s) 1084-1087, ISSN 0741-3106
Éditeur:
Institute of Electrical and Electronics Engineers
DOI:
10.1109/led.2019.2915118
Auteurs:
Carlos Navarro, Santiago Navarro, Carlos Marquez, Luca Donetti, Carlos Sampedro, Siegfried Karg, H. Riel, Francisco Gamiz
Publié dans:
IEEE Journal of the Electron Devices Society, Numéro 6/1, 2018, Page(s) 884-892, ISSN 2168-6734
Éditeur:
Institute of Electrical and Electronics Engineers Inc.
DOI:
10.1109/jeds.2018.2859233
Auteurs:
L. Donetti, C. Sampedro, F.G. Ruiz, A. Godoy, F. Gamiz
Publié dans:
Solid-State Electronics, Numéro 143, 2018, Page(s) 49-55, ISSN 0038-1101
Éditeur:
Pergamon Press Ltd.
DOI:
10.1016/j.sse.2018.02.004
Auteurs:
S. Cristoloveanu, K.H. Lee, M.S. Parihar, H. El Dirani, J. Lacord, S. Martinie, C. Le Royer, J.-Ch. Barbe, X. Mescot, P. Fonteneau, Ph. Galy, F. Gamiz, C. Navarro, B. Cheng, M. Duan, F. Adamu-Lema, A. Asenov, Y. Taur, Y. Xu, Y-T. Kim, J. Wan, M. Bawedin
Publié dans:
Solid-State Electronics, Numéro 143, 2018, Page(s) 10-19, ISSN 0038-1101
Éditeur:
Pergamon Press Ltd.
DOI:
10.1016/j.sse.2017.11.012
Auteurs:
Carlos Navarro, Joris Lacord, Mukta Singh Parihar, Fikru Adamu-Lema, Meng Duan, Noel Rodriguez, Binjie Cheng, Hassan El Dirani, Jean-Charles Barbe, Pascal Fonteneau, Maryline Bawedin, Campbell Millar, Philippe Galy, Cyrille Le Royer, Siegfried Karg, Paul Wells, Yong-Tae Kim, Asen Asenov, Sorin Cristoloveanu, Francisco Gamiz
Publié dans:
IEEE Transactions on Electron Devices, Numéro 64/11, 2017, Page(s) 4486-4491, ISSN 0018-9383
Éditeur:
Institute of Electrical and Electronics Engineers
DOI:
10.1109/ted.2017.2751141
Auteurs:
H. El Dirani, K.H. Lee, M.S. Parihar, J. Lacord, S. Martinie, J-Ch. Barbe, X. Mescot, P. Fonteneau, J.-E. Broquin, G. Ghibaudo, Ph. Galy, F. Gamiz, Y. Taur, Y.-T. Kim, S. Cristoloveanu, M. Bawedin
Publié dans:
Microelectronic Engineering, Numéro 178, 2017, Page(s) 245-249, ISSN 0167-9317
Éditeur:
Elsevier BV
DOI:
10.1016/j.mee.2017.05.047
Auteurs:
Carlos Navarro, Meng Duan, Mukta Singh Parihar, Fikru Adamu-Lema, Stefan Coseman, Joris Lacord, Kyunghwa Lee, Carlos Sampedro, Binjie Cheng, Hassan El Dirani, Jean-Charles Barbe, Pascal Fonteneau, Seong-Il Kim, Sorin Cristoloveanu, Maryline Bawedin, Campbell Millar, Philippe Galy, Cyrille Le Royer, Siegfried Karg, Heike Riel, Paul Wells, Yong-Tae Kim, Asen Asenov, Francisco Gamiz
Publié dans:
IEEE Transactions on Electron Devices, Numéro 64/12, 2017, Page(s) 4904-4909, ISSN 0018-9383
Éditeur:
Institute of Electrical and Electronics Engineers
DOI:
10.1109/ted.2017.2759308
Auteurs:
J. Lacord, S. Martinia, M.-S. Parihar, K. Lee, M. Bawedin, S. Cristoloveanu, Y. Taur, J.-Ch. Barbe
Publié dans:
2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2017, Page(s) 321-324, ISBN 978-4-86348-610-2
Éditeur:
IEEE
DOI:
10.23919/sispad.2017.8085329
Auteurs:
Francois Tcheme Wakam, Joris Lacord, Maryline Bawedin, Sebastien Martinie, Sorin Cristoloveanu, Jean-Charles Barbe
Publié dans:
2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2018, Page(s) 115-118, ISBN 978-1-5386-6790-3
Éditeur:
IEEE
DOI:
10.1109/SISPAD.2018.8551653
Auteurs:
Xingsheng Wang, Dave Reid, Liping Wang, Campbell Millar, Alexander Burenkov, Peter Evanschitzky, Eberhard Baer, Juergen Lorenz, Asen Asenov
Publié dans:
2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2016, Page(s) 303-306, ISBN 978-1-5090-0818-6
Éditeur:
IEEE
DOI:
10.1109/SISPAD.2016.7605207
Auteurs:
F. Tcheme Wakam, J. Lacord, S. Martinie, J.-Ch. Barbe, F. Tcheme Wakam, M. Bawedin, S. Cristoloveanu
Publié dans:
2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2017, Page(s) 329-332, ISBN 978-4-86348-610-2
Éditeur:
IEEE
DOI:
10.23919/SISPAD.2017.8085331
Auteurs:
S. Martinie, J. Lacord, O. Rozeau, M.-S. Parihar, Kyunghwa Lee, Maryline Bawedin, Sorin Cristoloveanu, Yuan Taur, J-C. Barbe
Publié dans:
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017, Page(s) 1-3, ISBN 978-1-5386-3766-1
Éditeur:
IEEE
DOI:
10.1109/S3S.2017.8309240
Auteurs:
C. Medina-Bailon, C. Sampedro, F. Gamiz, A. Godoy, L. Donetti
Publié dans:
2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2016, Page(s) 100-103, ISBN 978-1-4673-8609-8
Éditeur:
IEEE
DOI:
10.1109/ulis.2016.7440062
Auteurs:
F. Tcheme Wakam, J. Lacord, M. Bawedin, S. Martinie, S. Cristoloveanu, G. Ghibaudo, J.-Ch. Barbe
Publié dans:
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2018, Page(s) 1-4, ISBN 978-1-5386-4811-7
Éditeur:
IEEE
DOI:
10.1109/ULIS.2018.8354339
Auteurs:
Mukta Singh Parihar, Kyung Hwa Lee, Hyung Jin Park, Carlos Navarro, Joris Lacord, Francisco Gamiz, Philippe Galy, Sorin Cristoloveanu, Maryline Bawedin
Publié dans:
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2018, Page(s) 1-4, ISBN 978-1-5386-4811-7
Éditeur:
IEEE
DOI:
10.1109/ULIS.2018.8354341
Auteurs:
K. R. A. Sasaki, C. Navarro, M. Bawedin, F. Andrieu, J. A. Martino, S. Cristoloveanu
Publié dans:
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016, Page(s) 1-2, ISBN 978-1-5090-4391-0
Éditeur:
IEEE
DOI:
10.1109/S3S.2016.7804373
Auteurs:
Mukta Singh Parihar, Kyung Hwa Lee, Hassan El Dirani, Carlos Navarro, Joris Lacord, Sebastien Martinie, Jean-Charles Barbe, Pascal Fonteneau, Philippe Galy, Cyrille Le Royer, Xavier Mescot, Francisco Gamiz, Binjie Cheng, Asen Asenov, Yuan Taur, Mayline Bawedin, Sorin Cristoloveanu
Publié dans:
2017 IEEE International Memory Workshop (IMW), 2017, Page(s) 1-4, ISBN 978-1-5090-3274-7
Éditeur:
IEEE
DOI:
10.1109/IMW.2017.7939093
Auteurs:
Mukta Singh Parihar, Kyung Hwa Lee, Maryline Bawedin, Joris Lacord, Sebastien Martinie, Jean-Charles Barbe, Yue Xu, Yuan Taur, Sorin Cristoloveanu
Publié dans:
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, Page(s) 57-60, ISBN 978-1-5090-5313-1
Éditeur:
IEEE
DOI:
10.1109/ULIS.2017.7962600
Auteurs:
Hyungjin Park, Kyunghwa Lee, Jean-Pierre Colinge, Sorin Cristoloveanu
Publié dans:
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018, Page(s) 1-3, ISBN 978-1-5386-7627-1
Éditeur:
IEEE
DOI:
10.1109/S3S.2018.8640198
Auteurs:
Joris Lacord, Mukta Singh Parihar, Carlos Navarro, Francois Tcheme Wakam, Maryline Bawedin, Sorin Cristoloveanu, Fransisco Gamiz, Jean-Charles Barbe
Publié dans:
2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2018, Page(s) 198-201, ISBN 978-1-5386-6790-3
Éditeur:
IEEE
DOI:
10.1109/SISPAD.2018.8551674
Auteurs:
M. Bawedin, H. El Dirani, K. Lee, M.S. Parihar, J. Lacord, S. Martinie, C. Le Royer, J.-Ch. Barbe, X. Mescot, P. Fonteneau, Ph. Galy, F. Gamiz, C. Navarro, B. Cheng, A. Asenov, Y. Taur, S. Cristoloveanu
Publié dans:
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, Page(s) 51-52, ISBN 978-1-5090-5313-1
Éditeur:
IEEE
DOI:
10.1109/ULIS.2017.7962598
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