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Directly Modulated Lasers on Silicon

Periodic Reporting for period 1 - DIMENSION (Directly Modulated Lasers on Silicon)

Reporting period: 2016-02-01 to 2017-07-31

Optical interconnects are applied as active optical cables for rack-to-rack links in datacenters for cloud-computing, big data, analytics and high-performance computing. Transceivers with single mode silicon photonics (SiP) are emerging as alternative to multimode vertical-cavity surface-emitting lasers. Longer transmission distance and the integration of additional optical functionality drive this trend. While SiP enables passive optical functions, it lacks a solution for a fully CMOS compatible integrated laser source. Consequently, today’s commercial SiP-based transceivers consist of at least three discrete chips: a passive SiP chip, a laser and a (Bi)CMOS chip. Their packaging cost represents more than 60% of the total manufacturing expense. Also the laser takes a substantial part of the bill of materials. Furthermore, the discrete approach lacks design flexibility and functionality features that are required to further performance and density scaling of optical interconnects. Various III-V on silicon integration approaches are explored in the state-of-the-art. However, the concepts do not provide a full integration of the III-V functionality in the CMOS process.
DIMENSION establishes a truly integrated fully CMOS compatible electro-optical platform, extending the silicon (Bi)CMOS and SiP platform with III-V photonic functionality. After bonding and growing ultra-thin III-V structures onto the silicon front-end-of-line, the active optical functions are embedded in between the front-end and back-end of line. This offers great opportunities for new innovative devices and functions at chip-level but also for packaged devices. As processing takes place on silicon wafers, the cost of integrated devices, with CMOS, photonic and III-V functionality, is brought down to the cost of silicon volume manufacturing. Such a platform fosters Europe to take a leading position in the field of high functionality integrated photonics. Moreover, three project demonstrators are planned that adhere to standards such as IEEE802.3 25G optical components and low-power electronics, thus opening a viable route towards ultra-low-cost high-performance optical transceivers for a new era of datacentres and cloud systems.
The objectives for the first project period were concepts and final specifications for systems and components as well as first optical and electrical designs. All work packages have been started and are on track. No deviations have been observed yet.
In WP1 - Project management, the overall project coordination and communication were arranged. Three project meetings were organized. Webconferences among the project partners on a regular three-weekly basis are scheduled. A webpage has been created with periodic updates. A secured data sharing system is arranged for information and document exchange. The research data handling was defined in the data management plan. During the reported project period, 8 project deliverables with accompanying reports and 2 milestones were achieved.
In WP2 - System requirements, transceiver specifications and benefits evaluation, the system specifications and requirements have been derived on basis of standardization and applications. The three system demonstrators were studied with the focus on inter- and intra-data center communication. Different modulation formats (PAM-4 and coherent formats) have been listed which will be studied by system simulation. System and component modelling has been started for simulation which reveals the target component parameters for optimal system performance. The results are summarized in D2.1 and D2.2. Techno-economic evaluation and power consumption study of the transmission systems are in progress. Here, the system performance limitations for fixed grid, bit rate and transmission distance are identified.
In WP3 - Optical component design and fabrication, the fabrication of first SiP devices was successful and reveals good process control and fast turn-around time. Optical III-V to silicon couplers and higher order waveguide gratings were investigated to meet the critical dimensions of the silicon fabrication process. First III-V lasers were designed and experimentally studied. New approaches to achieve current confinement in the thin laser stacks for efficient electrical pumping were developed. First epitaxial stacks were grown and a good planarization process control and successful bonding was shown. Lasing was observed on the optically pumped devices. The electrically pumped devices show successful diode behaviour with corresponding electro-luminescence but have high turn-on voltage which finally led to an electrical break-down which needs to be resolved for the final implementation. The results are summarized in D3.1 report.
In WP4 - Electronic design and electro-optic integration, the access to the target technologies and the process flow for III-V laser on silicon integration have been arranged. Two modulator drivers were designed for segmented (under fabrication) and traveling wave modulators (tape-out in August 2017) to study performance trade-offs. Both designs are capable of 40 Gb/s and provide a differential output voltage swing of 7.6 Vpp while the segmented approach implies much higher power consumption. To achieve required coupling between the III-V device and Si waveguide the BiCMOS process was successfully adapted with an additional SiN layer.
In WP5 - Packaging and characterization and evaluation of demonstrators, first packaging concepts and roadmaps for component and system measurements have been established on basis of system and component specifications. For each of the three demonstrators a test board with embedded opto-electronic chips will be designed. Wire bonding capabilities are evaluated to achieve best HF and bias coupling. The opto-electronic devices will be first measured on chip. For the demonstration the chips will be packaged and connected to electrical and optical interfaces.
In WP6 - Dissemination, Standardization and Exploitation, many activities have been achieved so far: press releases, project introduction at several workshops and conferences, project webpage, dissemination kit and first scientific publications. To secur
The cost-effective integration of high-quality III-Vs on large-area silicon substrates remains one of the most challenging issues that must be solved to build a competitive III-V/Si photonics technology. So far, three major routes have been identified: thick buffers between Si and InGaAs, direct wafer bonding, growing InGaAs into high aspect-ratio trenches (ART). The drawbacks of those approaches are either high costs, non-versatile technology or high defect density, which is not usable for low-power and long life-time. In DIMENSION, a direct wafer bonding technology will first be used to reach an early demonstration of the III-V/Si photonic technology for further optimization. In parallel a radically new technique to integrate high-quality III-V materials on SiP component in a cost-efficient way is developed. This breakthrough technique is a selective epitaxy based method, leading to cost-effective, high quality and high versatile devices.
Integration concpet of active III-V components on silicon