Periodic Reporting for period 3 - DIMENSION (Directly Modulated Lasers on Silicon)
Reporting period: 2019-02-01 to 2020-09-30
DIMENSION establishes a truly integrated electro-optical platform, extending the silicon (Bi)CMOS and SiP platform with III-V photonic functionality. The III-V integration concept is fully CMOS compatible and offers fundamental advantages compared to state-of-the art integration approaches. After bonding and growing ultra-thin III-V structures onto the silicon front-end-of-line, the active optical functions are embedded in between the front-end and back-end of line. This offers great opportunities for new innovative devices and functions at the chip-level but also for the assembly of such silicon devices. As processing takes place on silicon wafers, this project has the unique opportunity to bring the cost of integrated devices, with CMOS, photonic and III-V functionality, down to the cost of silicon volume manufacturing. Such a platform has the potential to allow Europe to take a leading position in the field of high functionality integrated photonics. The project demonstrators adhere to optical components and low-power electronics, which will show that a monolithic CMOS-compatible integration process of active optical III-V components together with SiP and electrical circuits is possible. Such a ground-breaking integration technology opens a viable route towards ultra-low-cost high-performance optical transceivers for a new era of datacenters and cloud systems.
In conclusion, we have shown the principle CMOS-compatible integration technology of active III-V devices on Si BiCMOS. Using a limited BEOL, LED structures with luminescence were functional, but the full BiCMOS BEOL could not be finished to validate III-V embedding structures in (Bi)CMOS BEOL for short and fast electrical interconnects to the electrical devices. Also electrically pumped III-V on Si lasing at room temperature remains unsolved. However, many challenges to realize the new integration technology have been resolved and many building block have been investigated, realized and demonstrated, which include for example: the bonding and direct growth of ultra-thin III-V QW stacks on FEOL BiCMOS, efficient optical coupling between Si and III-V via a-Si waveguides and based on adiabatic mode conversion, laser feedback and passive optical structures in Si for minimum processing requirements on the III-V structure, CMOS-compatible contacts, and various current confinement and injection schemes.
Moreover, we have designed and verified many EPIC chips, like co-integrated drivers with modulators and photodetectors with transimpedance amplifiers, with improved performance. For the packaging of sub-assemblies and transceiver systems, improved and optimized techniques for wirebonding, optical alignment and optical coupling with high precision and low losses have been developed and applied. The EPIC designs and sub-assemblies have been successfully measured. All the project results have been intensively disseminated and will be exploited after the project end.
The second period of DIMENSION project has been started in August 2017. The work, communication and collaboration among the project partners continued. The focus was on further component designs, the further development of the III-V on Si technology and fabrication. The main outcomes of this phase are first component measurements and a first wafer run of III-V and Si components with the novel developed integration technology.
The third period of DIMENSION project has been started in February 2019. The work, communication and collaboration among the project partners continued and the project was finished in September 2020. The focus was on the finalization of the several components including the III-V light sources and the electro-photonic integrated circuits (EPIC). Those components were packaged on test sub-assemblies with coupling to optical fibers and fully characterized. Furthermore, the finalization of the full integration wafer run including III-V, SiP and electronic components (Run1), which was started in the second project phase, was intended for verification of the novel CMOS-compatible III-V on Si integration technology. As an outcome of the third project period, the entire project, the integration technology and its demonstrators are evaluated for future perspectives.