Billions of tiny computers that can sense and communicate from anywhere are coming online, creating the “Internet of Things” (IoT). As the IoT continues to expand, more and more devices need batteries and plugs. According to Gartner (www.gartner.com) there will be nearly 26 billion devices connected to the IoT by 2020. Therefore, together with improved batteries, advanced computation and communication must be delivered at extremely low-power consumption.
It is well-known that Single Electron Transistors (SET) are extremely low-energy dissipation devices. CMOS and SETs are complementary: SET is the champion of low-power consumption while CMOS advantages like high-speed, driving etc. compensate exactly for SET's intrinsic drawbacks. Unrivalled integration with high performance is expected for hybrid SET-CMOS architectures.Manufacturability is the roadblock for large-scale use of hybrid SET-CMOS architectures. To assure room temperature (RT) operation, single dots of diameters below 5 nm have to be fabri-cated, exactly located between source and drain with tunnel distances of a few nm. A reliable CMOS compatible process of co-fabrication of RT-SETs and FETs is not yet available.
IONS4SET will pave the way for fabrication of low-energy devices operating at RT using the discovery of a bottom-up self-assembly process. Lithography cannot deliver the feature sizes of 1…3 nm required for RT operation. IONS4SET will provide both, (i) controlled self-assembly of single ~ 2 nm Si dots and (ii) self-alignment of each nanodot with source and drain at tunneling distances of ~ 2 nm. The fabrication process of the Si nanodot involves (i) ion irradiation through a few tens of nm thin Si pillars with an embedded SiO2 layer and (ii) thermal activation of self-assembly. Dot self-assembly works for narrow pillars only, i.e. nanopillar fabrication is crucial for IONS4SET. Finally, a power saving hybrid SET/CMOS device with a vertical gate-all-around nanowire GAA-SET will be fabricated.
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