Periodic Reporting for period 2 - ARGO (WCET-Aware Parallelization of Model-Based Applications for Heterogeneous Parallel Systems)
Reporting period: 2017-07-01 to 2019-03-31
More and more safety-critical embedded electronic solutions are based on rapid, energy-efficient multi-core processors. Increased performance in real time systems and further reduction of costs without adversely affecting functional safety are two of the most important requirements of future applications in that area. This requires on the one hand real time capable multi-core processors to provide the required performance and on the other hand a holistic tool support to efficiently program such hardware. Multi-core systems are characterized by the accommodation of several processor cores on one chip. The cores work in parallel and, hence, reach a higher speed and performance. Programming of such heterogeneous multi-core processors is very complex. Moreover, the programs have to be tailored precisely to the target hardware and to fulfill the additional real-time requirements. The ARGO EU research project, named after the very quick vessel in Greek mythology, aimed at significantly facilitating programming by automatic parallelization of model-based applications and code generation. So far, a programmer had to adapt his code, i.e. the instructions for the computer, to the hardware architecture, which is associated with a high expenditure and prevents the code from being transferred to other architectures.
Under ARGO, a novel tool chain for programmers has been developed. Even without precise knowledge of the complex parallel processor hardware, the programmers can control the process of automatic parallelization in accordance with the requirements. This results in a significant improvement of performance and a reduction of costs. The ARGO tool chain can be used to manage the complexity of parallelization and adaptation to the target hardware in a largely automated manner with a small expenditure. Under the project, real-time-critical applications in the areas of real-time flight dynamics simulation and real-time image processing have been and evaluated by way of example.
At the end of the projects, the ARGO tool chain has been successfully demonstrated using two time critical applications from the aerospace and the industrial image-processing domain. As target hardware platforms for the tool chain, the consortium studied three different architectures and showed the extensibility towards additional platforms. The final ARGO demonstrators illustrate that both the development productivity and the real-time application performance can be improved using the ARGO tools in conjunction with model-based design principles and multi-core processing platforms.
To demonstrate the tool flow, the project consortium prototyped two time critical applications from the aerospace and the industrial image processing domain. The first use-case application developed by the project partner DLR is a Terrain Awareness and Warning System (TAWS), which warns the pilot of an aircraft if the air vehicle comes close to the terrain. The second use-case application was developed by the partner IIS and represents a polarization image processing system used for quality assurance in glass manufacturing processes.
The major part of research and development works flew into the ARGO toolchain prototype. To enable model-based design in the tool flow, the project partners Scilab and emmtrix Technologies developed front-end tools to transform the Scilab/Xcos code into the target language C. Further tool-chain steps to parallelize the generated C code have been researched and implemented by UR1, TWG and KIT. UR1 developed polyhedral transformations to improve parallelizability and data locality of the program. TWG contributed a WCET-aware scheduling module, which generates and optimizes the coarse-grained structure of the parallelized program. KIT provided parallel code generation components and fine-grained optimization steps for data management and synchronization placement. A cross-layer optimization module enables iterative optimization and user interaction by means of a comprehensive Graphical User Interface (GUI) developed by emmtrix.
UR1 developed the ARGO multi-core WCET analysis module, which utilizes the commercial tool aiT from the project partner AbsInt. The aiT tool itself has been extended in the project in order to generate additional information required for the multi-core analysis.
To import hardware information into the ARGO toolchain, KIT customized an Architecture Description Language (ADL) to provide detailed timing information. The developed ADL specification is an extension of existing industry standards.
Within the ARGO project, three hardware platforms have been studied as targets for the code generated by the ARGO tools. KIT created and customized a variant research platform InvasIC while the two commercial off-the-shelf platforms Kalray MPPA2 and Infineon Aurix have been studied as additional targets.
Another step beyond the state of the art are novel polyhedral loop transformations aiming for better worst-case performance by optimizing the program for more efficient memory usage especially when fast scratchpad memories are available in the target hardware.
Further progress has been made by investigating static mapping and scheduling optimization techniques for real-time parallel applications while considering interference on shared hardware resources like a shared main memory.
Progress beyond state of the art solutions has also been made in modelling and optimizing the data flow, memory usage and synchronization in parallel programs. Several of these improvements are not only limited to real-time applications but can also be beneficial for average-case parallelization tools.
Another main research field of ARGO are WCET analysis algorithms for multi-core processors. Here, the project made progress I) in defining an appropriate programming model for analyzable parallel multi-core programs, II) in developing algorithms to estimate the WCET of the parallel applications based on several single-core WCET analysis passes and III) modelling the timing properties of the target architectures in a suitable way.
The main expected impacts are to increase the adoption of multi-core processors and model-based design principles in time critical application areas.