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Rf Engineered substrates to FostER fEm performaNCE

Periodic Reporting for period 3 - REFERENCE (Rf Engineered substrates to FostER fEm performaNCE)

Reporting period: 2018-05-01 to 2019-04-30

The REFERENCE project aims to leverage a European leading edge Radio Frequency (RF) ecosystem based on RF Silicon On Insulator (SOI) disruptive technology, perceived as the most promising to address performance, cost and integration needs for RF Front End Modules (FEMs).
The project targets to develop over the next 3 years, innovative solutions from material, engineered substrates, process, design, metrology to system integration capable to address the unresolved 4G+ requirements for RF FEMs (data rate >1Gb/s) and pave the way to 5G.
The R&D and demonstration actions include:
• Development of innovative RFSOI substrates for 4G+ / 5G
• Move to 300 mm diameter
• Development of 4G+ / 5G RF-SOI devices with 2 major European foundries : analog in 200 mm 130nm technology, RF digital by combining RFSOI and FDSOI in 300 mm at 22nm;
• Innovative design for 4G+ /5G (analog and RF digital),
• Integration of several 4G+ FEM components on the same chip and demonstration System in Package Technology (SiP).
3 applications are investigated:
• Cellular / Iot : 4G+ RFSOI FEM demonstrator at SiP device level
• Automotive : 4G+ RF-SOI demonstrator at SiP device level
• Aviation: RF-SOI high data rate wireless communication module at system level; targeting a new frequency band for aeronautic.
The project is executed within 5 European countries, by on a strong complementary and well balanced consortium. It clearly aims to develop industrial solutions enabling European leadership and production.
Through this technology disruption, REFERENCE project addresses major thrusts for smart mobility, smart society, semiconductor processes, equipments, design technology and smart systems implementation, and support the societal challenges of smart transport, as well as secure and innovative society.
In the WP1: PCA was signed. Very active dissemination with 42 cumulated inititatives. Delays due to different reasons bring the consortium to propose an emndment with a 6 month extension request.

In the WP2: LMI has developed a brand new trap rich layer including carbon incorporation which has been transferred and tested successfully to a 300 mm epi tool. RF performances are not at the HD2 RF performances expected level. Soitec decided to focus on the improvement of defect quality of 200mm RF-SOI with RF performances HD2 of -90dbm in adequation with 4G/4G+ target. Siltronic has pursued the 300mm development of the 2nd generation of poly Si wafers including really high resistivity (> 8 kohm.cm) substrate.300mm first worldwide FD-TRSOI wafers were finally delivered to GF (The newly developed processed was done in collaboration with CEA-LETI and was using Siltronic Gen 2 poly Si wafers with high resistivity substrates.) Soitec has started the development of a new RF-PDSOI product with 4KA BOX targeting the Antenna Tuner market in collaboration with LETI.

In the WP4:
Wafer Level Fan-Out Packaging:
• RDL 3/3µm Line/Space (target <5/5µm) achieved with UV lithograpgy
• RDL vias of 10um achieved with Eximer Laser ablation and UV lithography
• WLFO packages <3580µm total thickness (target >400µm)
• Electromigration studies in High Density RDL (studies non-existing prior to Reference)
Aeronautic frequency band 4.2-4.4 GHz:
• First SoC SDR with Embedded 64 bit Linux

In the WP5: Work is progressing toward the planned targets. Significant progress has been reported on the understanding of TR material morphology, on the functionality of an advanced HDI sensor, its integration in a functional in-line characterization tool, on the characterization of the electrical response of TR layers. Reliability work has started and is heading toward producing a choice of test conditions that will later be applied to RFSOI substrates / TR layers.
Work is following schedule in most tasks. In T5.3 unscheduled developments were required to reduce the sensitivity of the tool to vibrations, delaying D5.8 by 6 months. This delay, however, is not expected to impact the remaining work.
WP2:
LMI has developed a new trap rich layer including Carbon incorporation
Soitec has achieved a 1st worldwide 200mm RF-SOI substrate with the highest resistivity in the handle base wafer with RF performances HD2 of -100dbm in adequation with 5G target.
Siltronic has also started the 300mm development of the 3rd generation of poly Si wafers including really high resistivity (> 20 kohm.cm) substrate.
Soitec has produced the first worldwide 300mm TR-FDSOI prototypes

WP3:
Task 3.3: The targeted LNA and switch targets to have 15dB power gain (SoA=12,6dB in SiGe) and 0,8dB Noise Figure (SoA=1,2dB in SiGe). Also during the first period the improvement on switch impedance tuning and front-end architecture improvement have been sent for patent.
Task 3.4: WAIC standard is a novel 4,2-4,4 GHz frequency band. So far no power amplifier exist optimized for this band and supporting the development of a low power solution. This task develops a first prototype based on LINC architecture (H9SOI-FEM) supported with freq. generation based on 22FDX.
Task 3.5: LMV cell incorporates all main receiver front end functions (LNA, VCO, & Down Conversion Mixer) and is capable of fulfilling BLE specifications at VDD=0.8V and power consumption < 500 uW. The design of PA/LNA/switch building blocks exploit advanced technology characteristics to enable low-power, high-frequency and highly integrated mm-wave multi-antenna array radio front-ends. No commercial solution existing on 22FDX