Ultra-Low Power and Highly-Scalable Interfaces for the Internet of Things

Información del proyecto

ULPIoT

Identificador del acuerdo de subvención: 703988

DOI

10.3030/703988

Proyecto cerrado

Fecha de la firma de la CE 14 Abril 2016

Fecha de inicio 1 Febrero 2017

Fecha de finalización 28 Febrero 2020

Financiado con arreglo a

• EXCELLENT SCIENCE - Marie Skłodowska-Curie Actions

Coste total

€ 247 728,60

Aportación de la UE

€ 247 728,60

Coordinado por

POLITECNICO DI TORINO
Italy

Periodic Reporting for period 2 - ULPIoT (Ultra-Low Power and Highly-Scalable Interfaces for the Internet of Things)

Período documentado: 2019-02-01 hasta 2020-01-31

Resumen del contexto y de los objetivos generales del proyecto

Internet of Things (IoT) is the vision of a world where pervasive integrated electronic systems embedded in everyday life objects are fully interconnected to collect, process and exchange useful information. Enabling the IoT requires energy-autonomous systems for distributed sensing and data acquisition. This imposes stringent constraints on cost, size and power for all on-chip sub-systems.

The low-cost requirement demands small area, low design effort, digital-like shrinkage across CMOS generations, and design/technology portability. A fully synthesizable Integrated Circuits (ICs) design approach meets all these requirements but is traditionally suitable for digital ICs only. Data processing is digital but most signals from the real-world are analog.

The ULPIoT project led by Dr. Orazio Aiello moves towards the idea of re-thinking analog and mixed-signal functions in digital terms, so that to address the fundamental challenges of energy-efficiency, size shrinking, technology portability and reduction of design effort in incoming IoT applications.
A novel design approach has been developed, which encompasses the fully automatic synthesis and layout generation of analog and mixed-signal blocks from high-level descriptions (e.g. in Verilog) at minimum effort and by the very same software tools and methodologies adopted in the digital IC flow. This approach leads to IC designs that are natively portable across technology nodes (e.g. from 40nm to 28nm) and highly reconfigurable, thus enabling dynamic energy-quality scaling, which is critical in tightly energy-constrained IoT application scenarios, as well as a low design effort and a fast time-to-market.
The project is based on a joint collaboration between the top ASEAN University, the National University of Singapore (NUS, where Dr. Aiello has spent the first two years of his MSCA Fellowship working with Prof. Massimo Alioto) and the Politecnico di Torino (where Dr. Aiello has worked with Prof. Paolo Crovetti).

The ULPIoT topic and the related high-quality scientific and technological cooperation with NUS, match with the strategic vision of catching up with the main competitors in ICT research and digital innovation.
The possibility to exploit the digital (automated) design flow even for analog building blocks can dramatically reduce the design effort of any system-on-chip that face with an analog signal. The increment of the overall scalability and the higher level of automation in IC design given by a digital-in-concept approach have a straightforward and broad impact on the cost of electronic devices everyone experiences daily.

Trabajo realizado desde el comienzo del proyecto hasta el final del período abarcado por el informe y los principales resultados hasta la fecha

The ULPIoT project strived successfully in increasing at most the level of automation in the design flow. The main IC analog building blocks have been implemented by means of a fully synthesizable design approach. Several test-chip have been taped-out in order to validate the innovative ideas thought test-chip measurements.

The main ULPIoT breakthroughs are the first fully synthesizable Digital-to-analog Converters (DACs) able to be designed with a fully automated digital design flow and the first pW-range wake-up oscillator for IoT sensor nodes able to operate from 0.3V to 1.8V avoidings the traditional need of additional power-hungry voltage regulation.

The proposed DACs significantly reduce the design effort compared to conventional analog design styles as they are based on a digital standard cells approach. This enables digital-like shrinkage across CMOS generations and hence low area at down-scaled technologies, as well as operation down to near-threshold voltages.
Three different versions have been proposed. The first DAC with a nominal resolution of 12-bit exhibits a graceful degradation under-voltage/frequency over scaling; The others are 16-bit and 12-bit versions pointing-out respectively only performance and area reduction.
All these characteristics make the proposed solutions highly suitable for the IoT nodes.
Slow oscillators that periodically wake up the sensor nodes are fundamental building blocks in the emerging Internet of Things (IoT). The proposed oscillator can work stand-alone, with no further voltage or current reference, and with a low-frequency sensitivity to the supply voltage. Thus, the actual power consumed by the always-on oscillator, and hence by the entire system is drastically reduced.

Another ULPIoT outcome is based on the automatized design approach employed to conceive analog comparison using only standard cells (logic gate). Also, digital-based operational amplifiers have been conceived.
Moreover, fully synthesizable Current- and Voltage-input ADCs architectures have been designed and tested.
As a further remark, the suitability of the employed methodologies for the processing in Deep Learning application has been explored.

The ULPIoT results have been presented in the premier conferences of “Circuit and System” (CAS) and “Solid State Circuit” (SSC) Societies (i.e. ISCAS and VLSI Symposium). The respective more extended works have been also published in top journal papers as Transaction of CAS and Journal of SSC.
As further dissemination activities, MSCA events have been held (https://sites.google.com/view/ulpiot/dissemination/seminars). Moreover, many technical seminars and tutorials at international conferences have been also held (https://sites.google.com/view/ulpiot/dissemination/tutorials).

As result of the scientific quality of the ULPIoT results, several international scientific presses have reported the value of the research outcomes developed in Singapore (as shown in the up-to-date ULPIoT’s press review: https://sites.google.com/view/ulpiot/press).
Moreover, a Semiconductor company (i.e. STMicroelectronics) has already expressed interest in ULPIoT results for the development of commercial and concrete IoT applications.

All the above-mentioned achievements are certainly proof of a remarkable scientific value of the ULPIoT project and commitment of the MSCA Fellow.

Avances que van más allá del estado de la técnica e impacto potencial esperado (incluida la repercusión socioeconómica y las implicaciones sociales más amplias del proyecto hasta la fecha)

"The increment of the overall scalability and the higher level of automation in IC design given by the proposed novel solutions have a straightforward and broad impact on the cost of electronic devices for IoT applications.
Moreover, a drastic reduction of static power consumption that maximizes the overall energy-efficiency of any electronic device is crucial in every IoT sensor node.

Thus, the project enable the IoT vision providing benefits in term of capability to reduce energy consumption. It accomplishes one of priorities of the European commission: consuming less energy in order to reduce pollution, preserve domestic energy sources and reducing the EU's need for energy imports.

ULPIoT intends to foster and re-enforce the European leadership in semiconductor research. Thus, potential users are firstly the semiconductor companies and then all those persons surrounded by ""smart devices"" in the incoming IoT era.
"

Photo of the MSCA Fellow Orazio Aiello in the Lab @ NUS