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Architectural Methodologies for Advanced Testing of VLSI Systems

Objective

ARCHIMEDES aims to answer the following questions:

- how to link architectural design with IC defects-based fault modelling and analysis
- how to merge in a single design the prerequisites for testing off-line (manufacturing) and online testing (lifetime)
- how to take advantage of both voltage testing and current testing
- how to extend to analogue and mixed signal testing what has been done during the last 20 years for digital testing, or what to do if no extension is possible.

No research is expected to be done on existing mature testing techniques. Advances in each area will cross-fertilised in order to obtain a global solution for the architectural synthesis of testable circuits.
The research has been carried out in order to bridge the gap between 2 apparently opposing trends in the very large scale integration (VLSI) design sphere: designing circuits from higher and higher levels in order to take advantage of the very large number of devices made available by the progress of technology; efficient testing based on integrated circuit (IC) defects fault models, which lead to nonaffordable times if testing is based on conventional test pattern generation for large designs. To this end, multiple testing methods targeted to multiple types of ICs are being developed using design for testability techniques.

Results have been obtained in many different facets including the following:
target structures for datapaths and controllers to be synthesized for offline testability;
regular structures like programmable logic arrays (PLA) designed for online testability;
the design of optimal analysers and the design of deterministic generators based on linear frequency sweep read only memory (LFSROM); a work on bismuth complementary metal oxide semiconductor (CMOS) for defect analysis;
work on bridging faults for layout design for testability work on analogue and mixed signal for fault modelling;
the use of current testing for analogue and mixed signal circuits;
the designs of analogue checkers for online testing, the design of built in current sensors.
APPROACH AND METHODS

Test pattern generation has now attained a good level, and professional CAD software exists to deal with quite large (though limited) parts of designs. Most parts can be dealt with by making them testable at the synthesis stage. To answer the questions raised above, ARCHIMEDES brings together experts on several individual testing methods, approaches and types in order to seek a global solution.

Specific areas of investigation include architectural synthesis, realistic analysis and innovative test techniques.

POTENTIAL

Research results are expected to contribute to the advance of the state of the art in many facets of testing. Applications are foreseen in industrial advanced products, making a contribution to the three major features governing the success or the failure of an electronic product in the market place: innovation, time-to-market, and quality.

Coordinator

Institut National Polytechnique de Grenoble
Address
46 Avenue Félix Viallet
38031 Grenoble
France

Participants (6)

INSTITUTO DE ENGENHARIA DE SISTEMAS E COMPUTADORES
Portugal
Address
Apartado 10105, Rua Alves Redol, 9
1017 Lisboa
UNIVERSITAT POLITECNICA DE CATALUNYA
Spain
Address
Diagonal 647
08028 Barcelona
UNIVERSITÄT GESAMTHOCHSCHULE SIEGEN
Germany
Address
Hoelderlinstraße 3
57076 Siegen
Università degli Studi di Bologna
Italy
Address
Viale Risorgimento 2
40136 Bologna
Universität Hannover
Germany
Address
Nienburger Straße 17
30167 Hannover
Université de Montpellier II (Université des Sciences et Techniques du Languedoc)
France
Address
Place Eugène Bataillon
34060 Montpellier