A Theory of Reliable Hardware

Project Information

ToRH

Grant agreement ID: 716562

DOI

10.3030/716562

Project closed

EC signature date 4 May 2017

Start date 1 August 2017

End date 31 July 2022

Funded under

• EXCELLENT SCIENCE - European Research Council (ERC)

Total cost

€ 1 472 000,00

EU contribution

€ 1 472 000,00

Coordinated by

CISPA - HELMHOLTZ-ZENTRUM FUR INFORMATIONSSICHERHEIT GGMBH
Germany

Periodic Reporting for period 4 - ToRH (A Theory of Reliable Hardware)

Reporting period: 2021-07-01 to 2022-07-31

Summary of the context and overall objectives of the project

The goal of the project is to develop hardware that is more reliable. This is achieved by developing a theory of fault-tolerant hardware, i.e. understanding fundamental principles in dealing with both transient and permanent faults of any kind. The developed ideas are then implemented to measure how successful they are in practice.

A main focus of the project is the development of highly reliable, accurate, and efficient clock generation and distribution methods. Traditional designs cannot cope with permanent faults and have limits in scalability, which we address by devising fault-tolerant distributed clocking methods. If successful, this enables faster, better, and cheaper computers. As computers (and computing devices) are omnipresent, this has the potential of large economical benefits.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

The project has resulted in many novel techniques for simultaneously achieving reliability and efficiency. Most prominently,

1. we developed a discrete abstraction allowing us to handle metastability - a problem caused by trying to read the value of a signal while being in transition - in an efficient manner without falling back to analog design,
2. we came up with several improved clock synchronization and distribution schemes, pushing the state of the art, and
3. we implemented some of these schemes, pushing towards their adoption in practice.

Concretely, our results form a solid theoretical foundation for more scalable hardware systems. To promote our insights, we are planning to found a start-up company whose goal is to transfer them into industry products.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

The abovementioned results all reach beyond the state of the art. Regarding metastability, before the project the only known way of dealing with metastability was to wait for it to disappear with sufficiently high probability. This caused large latencies, which we can avoid with our techniques in certain, highly relevant cases. Our fault-tolerant clock generation and distribution schemes offer the opportunity to completely redesign computer hardware in a much more robust and scalable manner. On the other hand, the tools we provide can be used for smaller changes whose benefits could be reaped immediately. This is demonstrated by our various implementations, which prove the practicality of our schemes and bring them closer to application.

TorH Picture