RESCUE aimed at and achieved progress beyond the state of the art in the following directions.
First, for the reliability, RESCUE fellows contributed to understanding failures and wear-out mechanisms, quantifying the impact, developing appropriate and accurate models to confidently predict the reliability. This resulted in efficient offline and online mitigation schemes, fault-tolerant designs, and tools that enabled reliability prediction and analysis at the design stage. Altogether, it will enhance the lifetime of today’s chips while keeping the failure rate low. An invention of an electronic circuit with integrated soft error monitors was protected by a European patent application with a RESCUE fellow and their supervisor being the first inventors.
Second, for the quality, RESCUE developed novel functional fault models and on-line test methods for nanoelectronic systems. In particular, ESRs focused on concurrent online test solutions, which can also cover temporary defects caused by the environment and permanent defects caused by wear-out of the nanoelectronic system. RESCUE developed novel error management schemes at the system level, which allowed setting seamless trade-offs between the targets of reliability and performance. As a result, the longevity of nanoelectronic systems is improved. Combined functional and extra-functional verification flows for identifying vulnerability to side-channel attacks (a security issue) in functionally correct designs were developed, including the analysis of the interdependency of quality, security and reliability in hardware neural networks.
Third, for security, ITN fellows aimed at researching and implementing new technologies for testing secure HW and addressed HW intrinsic security. The research handled nanoelectronic systems protection against data, design and functionality attacks while considering system’s reliability. In particular, the fellows built a complete static random access memory (SRAM) cell model for Physical Unclonable Functions (PUFs) analysis. The fellows performed the PUF reliability analysis for the latest manufacturing technology nodes down to 7nm that increased the community awareness of the PUF technology applicability. ITN fellows contributed to the study of practical optical fault injection attacks against state-of-the-art chips and identified important patterns and sensitive areas that should be considered by the research community. Furthermore, application of artificial intelligence and machine learning for fault injection attacks and countermeasures resulted in an innovative forward-looking solution of enabling detection of yet unknown fault attacks.
Fourth, for EDA tools and methodologies, ITN fellows aimed at validation and assessment of the proposed above techniques for reliability, quality and security. Their contributions included efficient fault-injection techniques, which reduce the time for the analysis of fault injection simulations by excluding irrelevant faults. The fault injection at mixed representation levels like Virtual Prototypes, register-transfer or gate-level netlists allow verification of the projects in different execution stages. The fellows have developed the first open-source benchmark family, i.e. AutoSoC (www.autosoc.org) for uniform evaluation of functional safety and security techniques for automotive nanoelectronics in Europe and worldwide. The combination of different novel approaches allowed achieving a higher confidence level in industry-scale functional safety EDA tools. Furthermore, an open-source EDA framework zamiaCAD for validating cutting-edge research approaches was developed and applied to reliability and quality techniques validation and enhancement.
