Periodic Reporting for period 2 - RESCUE (Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems Design)
Reporting period: 2019-04-01 to 2021-03-31
Today, nanoelectronic systems are at the core of all industry sectors and deployed in life-critical application domains, such as healthcare, transportation, automotive and security, serving societal needs in Europe. They are being combined into Internet-of-Things and Cyber-Physical Systems and, ultimately, represent the physical backbone of our increasingly digitised world. Here, the impact and consequences of in-field failures, security attacks or hardware defects can be catastrophic. At the same time, they are getting very hard to avoid due to the trends of extreme complexity and miniaturisation at the doorstep of physical limits.
The objective is, first, to address the demanding and mutually dependent aspects of nanoelectronic systems design, i.e. reliability, security and quality, as well as corresponding electronic design automation tools. This will rescue and enhance design of complex systems at the next generation nanoelectronics technologies. Second, it is to provide early-stage researchers with innovative cross-sectoral training in the involved disciplines and beyond, such that they will be not only able to face today and future challenges in nanoelectronics design but also be innovative, creative, and more importantly - have an entrepreneurial mentality. The latter helps to compile ideas into products and services for EU economic and social benefits.
RESCUE successfully addressed boosting Europe’s capabilities and leadership in nanoelectronics design and creating qualified workforce and knowledge for the industry. The consortium consisting of leading European research groups was excellently balanced in terms of academic and industrial training and research facilities. The ITN was efficient in tackling the interdependent challenges in a holistic manner and training 15 new excellent interdisciplinary professionals.
First, for the reliability, RESCUE fellows contributed to understanding failures and wear-out mechanisms, quantifying the impact, developing appropriate and accurate models to confidently predict the reliability. This resulted in efficient offline and online mitigation schemes, fault-tolerant designs, and tools that enabled reliability prediction and analysis at the design stage. Altogether, it will enhance the lifetime of today’s chips while keeping the failure rate low. An invention of an electronic circuit with integrated soft error monitors was protected by a European patent application with a RESCUE fellow and their supervisor being the first inventors.
Second, for the quality, RESCUE developed novel functional fault models and on-line test methods for nanoelectronic systems. In particular, ESRs focused on concurrent online test solutions, which can also cover temporary defects caused by the environment and permanent defects caused by wear-out of the nanoelectronic system. RESCUE developed novel error management schemes at the system level, which allowed setting seamless trade-offs between the targets of reliability and performance. As a result, the longevity of nanoelectronic systems is improved. Combined functional and extra-functional verification flows for identifying vulnerability to side-channel attacks (a security issue) in functionally correct designs were developed, including the analysis of the interdependency of quality, security and reliability in hardware neural networks.
Third, for security, ITN fellows aimed at researching and implementing new technologies for testing secure HW and addressed HW intrinsic security. The research handled nanoelectronic systems protection against data, design and functionality attacks while considering system’s reliability. In particular, the fellows built a complete static random access memory (SRAM) cell model for Physical Unclonable Functions (PUFs) analysis. The fellows performed the PUF reliability analysis for the latest manufacturing technology nodes down to 7nm that increased the community awareness of the PUF technology applicability. ITN fellows contributed to the study of practical optical fault injection attacks against state-of-the-art chips and identified important patterns and sensitive areas that should be considered by the research community. Furthermore, application of artificial intelligence and machine learning for fault injection attacks and countermeasures resulted in an innovative forward-looking solution of enabling detection of yet unknown fault attacks.
Fourth, for EDA tools and methodologies, ITN fellows aimed at validation and assessment of the proposed above techniques for reliability, quality and security. Their contributions included efficient fault-injection techniques, which reduce the time for the analysis of fault injection simulations by excluding irrelevant faults. The fault injection at mixed representation levels like Virtual Prototypes, register-transfer or gate-level netlists allow verification of the projects in different execution stages. The fellows have developed the first open-source benchmark family, i.e. AutoSoC (www.autosoc.org) for uniform evaluation of functional safety and security techniques for automotive nanoelectronics in Europe and worldwide. The combination of different novel approaches allowed achieving a higher confidence level in industry-scale functional safety EDA tools. Furthermore, an open-source EDA framework zamiaCAD for validating cutting-edge research approaches was developed and applied to reliability and quality techniques validation and enhancement.