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Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems Design

Deliverables

ESR4.1 IRP EDA tools and methodologies for reliable nanoelectronic systems

"D4.1 reports on progress of WP4 IRP ""EDA tools and methodologies for reliable nanoelectronic systems"" corresponding to task T4.1. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR4.3 IRP Open-source EDA tools for design quality and reliability using zamiaCAD

"D4.3 reports on progress of WP4 IRP ""Open-source EDA tools for design quality and reliability using zamiaCAD"" corresponding to task T4.3. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR3.2 IRP Design approaches for tamper resistant crypto implementations

"D3.2 reports on progress of WP3 IRP ""Design approaches for tamper resistant crypto implementations"" corresponding to task T3.2. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR1.3 IRP HW/SW fault tolerance methods driven by reliability and timing constraints

"D1.3 reports on progress of WP1 IRP ""HW/SW fault tolerance methods driven by reliability and timing constraints"" corresponding to task T1.3. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR3.3 IRP Side-channel and Fault Attack resistant security primitives design

"D3.3 reports on progress of WP3 IRP ""Side-channel and Fault Attack resistant security primitives design"" corresponding to task T3.3. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

Comprehensive Communication Plan

Comprehensive Communication Plan to map main target groups and dissemination plan.

ESR2.2 IRP Innovative real-time operating system for error management for single- and multi-core units

"D2.2 reports on progress of WP2 IRP ""Innovative real-time operating system for error management for single- and multi-core units"" corresponding to task T2.2. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR4.2 IRP EDA tools and methodologies for high quality nanoelectronic systems

"D4.2 reports on progress of WP4 IRP ""EDA tools and methodologies for high quality nanoelectronic systems"" corresponding to task T4.2. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR1.5 IRP Reliable operation infrastructure for dynamic, high-dependability applications

"D1.1 reports on progress of WP1 IRP ""Reliable operation infrastructure for dynamic, high-dependability applications"" corresponding to task T1.1. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR1.4 IRP Techniques for detecting permanent faults during the operational phase

"D1.4 reports on progress of WP1 IRP ""Techniques for detecting permanent faults during the operational phase"" corresponding to task T1.4. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR3.1 IRP A novel Physical Unclonable Functions technology

"D3.1 reports on progress of WP3 IRP ""A novel Physical Unclonable Functions technology"" corresponding to task T3.1. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR1.2 IRP Adaptive methods for fault tolerant embedded systems

"D1.2 reports on progress of WP1 IRP ""Adaptive methods for fault tolerant embedded systems"" corresponding to task T1.2. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR2.1 IRP Effective techniques for secure and reliable systems validation

"D2.1 reports on progress of WP2 IRP ""Effective techniques for secure and reliable systems validation"" corresponding to task T2.1. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

Report on recruitment process

Report on recruitment process and the recruited fellows enrolment in PhD programme

ESR1.1 IRP Reliability analysis methods and models of memory devices

"D1.1 reports on progress of WP1 IRP ""Reliability analysis and modelling of memory devices"" corresponding to task T1.1. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

Supervisory board of the network

Establish the Supervisory board of the network.

ESR2.3 IRP A synthetic, hierarchical abstraction approach for modelling and managing complex systems quality and reliability

"D2.3 reports on progress of WP2 IRP ""A synthetic, hierarchical abstraction approach for modelling and managing complex systems quality and reliability"" corresponding to task T2.3. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR2.4 IRP Design errors verification and debug methods for complex nanoelectronic systems

"D2.4 reports on progress of WP2 IRP ""Design errors verification and debug methods for complex nanoelectronic systems"" corresponding to task T2.4. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

Website, project logo and wiki-type online collaboration tool

Website, project logo and wiki-type online collaboration tool as for main dissemination.

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Publications

Engineering of Cross-Layer Fault Tolerance In Multiprocessing Systems

Author(s): J.-C. Chen, M. Krstic
Published in: Proc. 8th Biannual European - Latin American Summer School on Design, Test and Reliability, Issue 20-22 June 2018, 2018

About the functional test of the GPGPU scheduler

Author(s): B. Du, Josie E. Rodriguez Condia, M. Sonza Reorda, L. Sterpone
Published in: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), Issue Hotel Cap Roig, Platja d’Aro, Costa Brava, Spain, July 2-4, 2018, 2018, Page(s) 85-90
DOI: 10.1109/IOLTS.2018.8474174

On the functional test of the GPGPU scheduler

Author(s): Josie E. Rodriguez Condia, B. Du, M. Sonza Reorda, L. Sterpone
Published in: A workshop on Self-driving Cars and Reliability, Rutherford Appleton Laboratory, Harwell Campus, 2018

A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks

Author(s): Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero
Published in: 2018 IEEE International Test Conference in Asia (ITC-Asia), 2018, Page(s) 55-60
DOI: 10.1109/ITC-Asia.2018.00020

Optical Fault Injections: a Setup Comparison

Author(s): D. Petryk, Z. Dyka, P. Langendörfer
Published in: Proc. 8th Biannual European - Latin American Summer School on Design, Test and Reliability, Issue 20-22 June 2018, 2018

Optical Fault Injections: Most Often Used Setups

Author(s): D. Petryk, Z. Dyka, P. Langendörfer
Published in: Proc. 29th Crypto-Day 2018, 2018
DOI: 10.18420/cdm-2018-29-11

Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262

Author(s): F. Augusto da Silva, A. C. Bagbaba, S. Hamdioui and C. Sauer
Published in: 2018 Design and Verification conference Europe (DVCON-Europe), 2018
DOI: 10.5281/zenodo.3361533

Improving the Confidence Level in Functional Safety Simulation Tools for ISO 26262

Author(s): A. C. Bagbaba, F. Augusto da Silva, C. Sauer
Published in: 2018 Design and Verification conference Europe (DVCON-Europe), 2018
DOI: 10.5281/zenodo.3361607

Single Event Characterization of a Xilinx UltraScale+ MP-SoC FPGA

Author(s): Thomas Lange, Maximilien Glorieux, Adrian Evans, A-Duong In, Dan Alexandrescu, Cesar Boatella-Polo, Carlos Urbina Ortega, Véronique Ferlet-Cavrois, Maris Tali, Rubén Garcı́a Alı́a
Published in: 2018 ESA/ESTEC Space FPGA Users Workshop (SEFUW), 2018

A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs

Author(s): Luca Sterpone, Sarah Azimi, Ludovica Bozzoli, Boyang Du, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Cesar Boatella Polo, David Merodio Codinachs
Published in: 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2018, Page(s) 120-126
DOI: 10.1109/AHS.2018.8541474

DFT Scheme for Hard-to-Detect Faults in FinFET SRAM

Author(s): Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Moritz Fieback, Leticia Bolzani Poehls, Said Hamdioui
Published in: Proc. IEEE European Test Symposium 2019 (in press), 2019

On the evaluation of SEU effects in GPGPUs

Author(s): B. Du, Josie E. Rodriguez Condia, M. Sonza Reorda, L. Sterpone
Published in: 2019 IEEE Latin American Test Symposium (LATS), 2019, Page(s) 1-6
DOI: 10.1109/latw.2019.8704643

An extended GPGPU model to support detailed reliability analysis

Author(s): Josie E. Rodriguez Condia, Matteo Sonza Reorda
Published in: SELSE-15: The 15th Workshop on Silicon Errors in Logic – System Effects, Issue 27-28 March 2019, Stanford, California, USA, 2019

IN-FIELD GPGPU TEST WITH SBST TECHNIQUES

Author(s): B. Du, Josie E. Rodriguez Condia, M. Sonza Reorda, L. Sterpone
Published in: NVIDIA GPU Tecnology Conference (GTC Europe 2018), Issue 23-25 October, 2018, Munich, Germany, 2018

A New Technique to Generate Test Sequences for Reconfigurable Scan Networks

Author(s): Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero
Published in: 2018 IEEE International Test Conference (ITC), 2018, Page(s) 1-9
DOI: 10.1109/test.2018.8624742

Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks

Author(s): A. Damljanovic, A. Jutman, G. Squillero and A. Tsertov
Published in: Proc. IEEE European Test Symposium 2019 (in press), 2019
DOI: 10.5281/zenodo.3362602

Comparing different approaches to the test of Reconfigurable Scan Networks

Author(s): R. Cantoro, A.Damljanovic. M. Sonza Reorda and G. Squillero
Published in: 2018 3rd International Test Standards Application Workshop (TESTA), 2018

Towards Multidimensional Verification: Where Functional Meets Non-Functional

Author(s): Maksim Jenihhin, Xinhui Lai, Tara Ghasempouri, Jaan Raik
Published in: 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2018, Page(s) 1-7
DOI: 10.1109/norchip.2018.8573495

Mixed-level identification of fault redundancy in microprocessors

Author(s): Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gursoy, Jaan Raik
Published in: 2019 IEEE Latin American Test Symposium (LATS), 2019, Page(s) 1-6
DOI: 10.1109/latw.2019.8704591

Software-Based Mitigation for Memory Address Decoder Aging

Author(s): D.H.P. Kraak, C.C. Gursoy, I.O. Agbo, M. Taouil, M. Jenihhin, J. Raik, S. Hamdioui
Published in: 2019 IEEE Latin American Test Symposium (LATS), 2019, Page(s) 1-6
DOI: 10.1109/latw.2019.8704595

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors

Author(s): Adeboye Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gursoy, Jaan Raik
Published in: Proc. IEEE European Test Symposium 2019 (in press), 2019

RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality

Author(s): Heinrich Theodor Vierhaus, Maksim Jenihhin, Matteo Sonza Reorda
Published in: 2018 12th European Workshop on Microelectronics Education (EWME), 2018, Page(s) 45-50
DOI: 10.1109/ewme.2018.8629465

Soft-Error Rate Due to Single-Event Transients in Clock Distribution Networks

Author(s): Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
Published in: 8th Biannual European - Latin American Summer School on Design, Test and Reliability, Issue 20-22 June 2018, 2018

Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits

Author(s): Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
Published in: SELSE-15: The 15th Workshop on Silicon Errors in Logic – System Effects, Issue 27-28 March 2019, 2019

Application of Graph Neural Network for Estimating Probabilistic Inferences in the Combinational Circuits (workshop poster with abstract)

Author(s): Aneesh Balakrishnan
Published in: Proc. 8th Biannual European - Latin American Summer School on Design, Test and Reliability, Issue 20-22 June 2018, 2018