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Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems Design

Deliverables

ESR4.1 IRP EDA tools and methodologies for reliable nanoelectronic systems

"D4.1 reports on progress of WP4 IRP ""EDA tools and methodologies for reliable nanoelectronic systems"" corresponding to task T4.1. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR4.3 IRP Open-source EDA tools for design quality and reliability using zamiaCAD

"D4.3 reports on progress of WP4 IRP ""Open-source EDA tools for design quality and reliability using zamiaCAD"" corresponding to task T4.3. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR3.2 IRP Design approaches for tamper resistant crypto implementations

"D3.2 reports on progress of WP3 IRP ""Design approaches for tamper resistant crypto implementations"" corresponding to task T3.2. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR1.3 IRP HW/SW fault tolerance methods driven by reliability and timing constraints

"D1.3 reports on progress of WP1 IRP ""HW/SW fault tolerance methods driven by reliability and timing constraints"" corresponding to task T1.3. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR3.3 IRP Side-channel and Fault Attack resistant security primitives design

"D3.3 reports on progress of WP3 IRP ""Side-channel and Fault Attack resistant security primitives design"" corresponding to task T3.3. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

Comprehensive Communication Plan

Comprehensive Communication Plan to map main target groups and dissemination plan.

ESR2.2 IRP Innovative real-time operating system for error management for single- and multi-core units

"D2.2 reports on progress of WP2 IRP ""Innovative real-time operating system for error management for single- and multi-core units"" corresponding to task T2.2. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR4.2 IRP EDA tools and methodologies for high quality nanoelectronic systems

"D4.2 reports on progress of WP4 IRP ""EDA tools and methodologies for high quality nanoelectronic systems"" corresponding to task T4.2. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR1.5 IRP Reliable operation infrastructure for dynamic, high-dependability applications

"D1.1 reports on progress of WP1 IRP ""Reliable operation infrastructure for dynamic, high-dependability applications"" corresponding to task T1.1. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR1.4 IRP Techniques for detecting permanent faults during the operational phase

"D1.4 reports on progress of WP1 IRP ""Techniques for detecting permanent faults during the operational phase"" corresponding to task T1.4. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

Report on Dissemination and Communication activities

Report on dissemination and Communication activities throughout the whole project.

ESR3.1 IRP A novel Physical Unclonable Functions technology

"D3.1 reports on progress of WP3 IRP ""A novel Physical Unclonable Functions technology"" corresponding to task T3.1. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR1.2 IRP Adaptive methods for fault tolerant embedded systems

"D1.2 reports on progress of WP1 IRP ""Adaptive methods for fault tolerant embedded systems"" corresponding to task T1.2. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

Reports on training events

Brief reports presenting the main training outcomes. Intermediate versions of the deliverable are due by M18 and M30.

ESR2.1 IRP Effective techniques for secure and reliable systems validation

"D2.1 reports on progress of WP2 IRP ""Effective techniques for secure and reliable systems validation"" corresponding to task T2.1. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

Report on recruitment process

Report on recruitment process and the recruited fellows enrolment in PhD programme

ESR1.1 IRP Reliability analysis methods and models of memory devices

"D1.1 reports on progress of WP1 IRP ""Reliability analysis and modelling of memory devices"" corresponding to task T1.1. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

Supervisory board of the network

Establish the Supervisory board of the network.

ESR2.3 IRP A synthetic, hierarchical abstraction approach for modelling and managing complex systems quality and reliability

"D2.3 reports on progress of WP2 IRP ""A synthetic, hierarchical abstraction approach for modelling and managing complex systems quality and reliability"" corresponding to task T2.3. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

ESR2.4 IRP Design errors verification and debug methods for complex nanoelectronic systems

"D2.4 reports on progress of WP2 IRP ""Design errors verification and debug methods for complex nanoelectronic systems"" corresponding to task T2.4. To monitor the progress of the IRP implementation, the deliverable has 3 deadlines for intermediate versions at M15, M27 and M41 corresponding to milestones MS5, MS7, MS10."

Website, project logo and wiki-type online collaboration tool

Website, project logo and wiki-type online collaboration tool as for main dissemination.

Articles published

40 scientific articles, 10 technical reports and 4 popular science articles will be published.

Publications

New categories of Safe Faults in a processor-based Embedded System

Author(s): C. Gursoy, M. Jenihhin, A. S. Oyeniran, D. Piumatti, J. Raik, M. Sonza Reorda, R. Ubar
Published in: 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2019, Page(s) 1-4
DOI: 10.1109/ddecs.2019.8724642

Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs

Author(s): Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Sandro Sartoni, Riccardo Cantoro, Matteo Sonza Reorda, Said Hamdioui, Christian Sauer
Published in: 2020 IEEE European Test Symposium (ETS), 2020, Page(s) 1-6
DOI: 10.1109/ets48528.2020.9131568

Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features

Author(s): Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
Published in: 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2020, Page(s) 1-7
DOI: 10.1109/iolts50870.2020.9159751

A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs

Author(s): Guilherme Cardoso Medeiros, Cemil Cem Gursoy, Lizhou Wu, Moritz Fieback, Maksim Jenihhin, Mottaqiallah Taouil, Said Hamdioui
Published in: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, Page(s) 792-797
DOI: 10.23919/date48585.2020.9116278

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

Author(s): Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
Published in: 2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), 2019, Page(s) 1-6
DOI: 10.1109/dtis.2019.8735052

Untestable faults identification in GPGPUs for safety-critical applications

Author(s): Josie E. Rodriguez Condia, Felipe A. Da Silva, S. Hamdioui, C. Sauer, M. Sonza Reorda
Published in: 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019, Page(s) 570-573
DOI: 10.1109/icecs46596.2019.8964677

On the in-field test of the GPGPU scheduler memory

Author(s): Stefano di Carlo, Josie E. Rodriguez Condia, Matteo Sonza Reorda
Published in: 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2019, Page(s) 1-6
DOI: 10.1109/ddecs.2019.8724672

Real-Time Dynamic Hardware Reconfiguration for Processors with Redundant Functional Units

Author(s): Randolf Rotta, Raphael Segabinazzi Ferreira, Jorg Nolte
Published in: 2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC), 2020, Page(s) 154-155
DOI: 10.1109/isorc49007.2020.00035

"""Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits"""

Author(s): T. Lange, A. Balakrishnan, M. Glorieux, D. Alexandrescu, L. Sterpone
Published in: 2019

Metal Fillers as Potential Low Cost Countermeasure against Optical Fault Injection Attacks

Author(s): Dmytro Petryk, Zoya Dyka, Jens Katzer, Peter Langendorfer
Published in: 2020 IEEE East-West Design & Test Symposium (EWDTS), 2020, Page(s) 1-6
DOI: 10.1109/ewdts50664.2020.9225092

Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices

Author(s): Xinhui Lai, Maksim Jenihhin, Georgios Selimis, Sven Goossens, Roel Maes, Kolin Paul
Published in: 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC), 2020, Page(s) 16-21
DOI: 10.1109/vlsi-soc46417.2020.9344071

Detecting Random Read Faults to Reduce Test Escapes in FinFETSRAMs

Author(s): G. C. Medeiros, M. Fieback, M. Taouil, L. B. Poehls, and S. Hamdioui
Published in: 2021

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems

Author(s): M. Jenihhin, S. Hamdioui, M. Sonza Reorda, M. Krstic, P. Langendorfer, C. Sauer, A. Klotz, M. Huebner, J. Nolte, H. T. Vierhaus, G. Selimis, D. Alexandrescu, M. Taouil, G. J. Schrijen, J. Raik, L. Sterpone, G. Squillero, Z. Dyka
Published in: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, Page(s) 388-393
DOI: 10.23919/date48585.2020.9116558

Hardware Accelerator Design with Supervised Machine Learning for Solar Particle Event Prediction

Author(s): J. Chen, T. Lange, M. Andjelkovic, A. Simevski, M. Krstic
Published in: 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2020, Page(s) 1-6
DOI: 10.1109/dft50435.2020.9250856

Testing the Divergence Stack Memory on GPGPUs: A Modular in-Field Test Strategy

Author(s): Josie E Rodriguez Condia, M. Sonza Reorda
Published in: 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC), 2020, Page(s) 153-158
DOI: 10.1109/vlsi-soc46417.2020.9344088

Design and Verification of an open-source SFU model for GPGPUs

Author(s): Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Cristhian-Fernando Moreno-Manrique, Matteo Sonza Reorda
Published in: 2020 17th Biennial Baltic Electronics Conference (BEC), 2020, Page(s) 1-6
DOI: 10.1109/bec49624.2020.9276748

On the testing of special memories in GPGPUs

Author(s): Josie E. Rodriguez Condia, Matteo Sonza Reorda
Published in: 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2020, Page(s) 1-6
DOI: 10.1109/iolts50870.2020.9159711

Efficient Fault Injection based on Dynamic HDL Slicing Technique

Author(s): Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer
Published in: 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019, Page(s) 52-53
DOI: 10.1109/iolts.2019.8854419

Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU

Author(s): Marcio M. Goncalves, Jose Rodrigo Azambuja, Josie E. R. Condia, Matteo Sonza Reorda, Luca Sterpone
Published in: 2020 IEEE Latin-American Test Symposium (LATS), 2020, Page(s) 1-6
DOI: 10.1109/lats49555.2020.9093682

A dynamic reconfiguration mechanism to increase the reliability of GPGPUs

Author(s): Josie E. Rodriguez Condia, Pierpaolo Narducci, M. Sonza Reorda, L. Sterpone
Published in: 2020 IEEE 38th VLSI Test Symposium (VTS), 2020, Page(s) 1-6
DOI: 10.1109/vts48691.2020.9107572

On NBTI-induced Aging Analysis in IEEE 1687 Reconfigurable Scan Networks

Author(s): Aleksa Damljanovic, Giovanni Squillero, Cemil Cem Guursoy, Maksim Jenihhin
Published in: 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, Page(s) 335-340
DOI: 10.1109/vlsi-soc.2019.8920313

Run-time Hardware Reconfiguration of Functional Units to Support Mixed-Critical Applications

Author(s): Raphael Segabinazzi Ferreira, Jorg Nolte, Fabian Vargas, Nevin George, Michael Hubner
Published in: 2020 IEEE Latin-American Test Symposium (LATS), 2020, Page(s) 1-6
DOI: 10.1109/lats49555.2020.9093692

Enabling Cross-Layer Reliability and Functional Safety Assessment Through ML-Based Compact Models

Author(s): Dan Alexandrescu, Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux
Published in: 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2020, Page(s) 1-6
DOI: 10.1109/iolts50870.2020.9159750

A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs

Author(s): Josie E. Rodriguez Condia, Pierpaolo Narducci, M. Sonza Reorda, L. Sterpone
Published in: 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2020, Page(s) 1-6
DOI: 10.1109/ddecs50862.2020.9095665

Combining Fault Analysis Technologies for ISO26262 Functional Safety Verification

Author(s): Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Said Hamdioui, Christian Sauer
Published in: 2019 IEEE 28th Asian Test Symposium (ATS), 2019, Page(s) 129-1295
DOI: 10.1109/ats47505.2019.00024

Analyzing the Sensitivity of GPU Pipeline Registers to Single Events Upsets

Author(s): Josie E. Rodriguez Condia, Marcio M. Goncalves, Jose Rodrigo Azambuja, Matteo Sonza Reorda, Luca Sterpone
Published in: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, Page(s) 380-385
DOI: 10.1109/isvlsi49217.2020.00076

Testing permanent faults in pipeline registers of GPGPUs: A multi-kernel approach

Author(s): Josie E. Rodriguez Condia, Matteo Sonza Reorda
Published in: 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019, Page(s) 97-102
DOI: 10.1109/iolts.2019.8854463

Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing

Author(s): Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer
Published in: 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2019, Page(s) 1-7
DOI: 10.1109/norchip.2019.8906932

A Benchmark Suite of RT-level Hardware Trojans for Pipelined Microprocessor Cores

Author(s): Aleksa Damljanovic, Annachiara Ruospo, Ernesto Sanchez, Giovanni Squillero
Published in: 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2021, Page(s) 51-56
DOI: 10.1109/ddecs52668.2021.9417061

Engineering of Cross-Layer Fault Tolerance In Multiprocessing Systems

Author(s): J.-C. Chen, M. Krstic
Published in: Proc. 8th Biannual European - Latin American Summer School on Design, Test and Reliability, Issue 20-22 June 2018, 2018

About the functional test of the GPGPU scheduler

Author(s): B. Du, Josie E. Rodriguez Condia, M. Sonza Reorda, L. Sterpone
Published in: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), Issue Hotel Cap Roig, Platja d’Aro, Costa Brava, Spain, July 2-4, 2018, 2018, Page(s) 85-90
DOI: 10.1109/IOLTS.2018.8474174

On the functional test of the GPGPU scheduler

Author(s): Josie E. Rodriguez Condia, B. Du, M. Sonza Reorda, L. Sterpone
Published in: A workshop on Self-driving Cars and Reliability, Rutherford Appleton Laboratory, Harwell Campus, 2018

A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks

Author(s): Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero
Published in: 2018 IEEE International Test Conference in Asia (ITC-Asia), 2018, Page(s) 55-60
DOI: 10.1109/ITC-Asia.2018.00020

Optical Fault Injections: a Setup Comparison

Author(s): D. Petryk, Z. Dyka, P. Langendörfer
Published in: Proc. 8th Biannual European - Latin American Summer School on Design, Test and Reliability, Issue 20-22 June 2018, 2018

Optical Fault Injections: Most Often Used Setups

Author(s): D. Petryk, Z. Dyka, P. Langendörfer
Published in: Proc. 29th Crypto-Day 2018, 2018
DOI: 10.18420/cdm-2018-29-11

Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262

Author(s): F. Augusto da Silva, A. C. Bagbaba, S. Hamdioui and C. Sauer
Published in: 2018 Design and Verification conference Europe (DVCON-Europe), 2018
DOI: 10.5281/zenodo.3361533

Improving the Confidence Level in Functional Safety Simulation Tools for ISO 26262

Author(s): A. C. Bagbaba, F. Augusto da Silva, C. Sauer
Published in: 2018 Design and Verification conference Europe (DVCON-Europe), 2018
DOI: 10.5281/zenodo.3361607

Single Event Characterization of a Xilinx UltraScale+ MP-SoC FPGA

Author(s): Thomas Lange, Maximilien Glorieux, Adrian Evans, A-Duong In, Dan Alexandrescu, Cesar Boatella-Polo, Carlos Urbina Ortega, Véronique Ferlet-Cavrois, Maris Tali, Rubén Garcı́a Alı́a
Published in: 2018 ESA/ESTEC Space FPGA Users Workshop (SEFUW), 2018

A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs

Author(s): Luca Sterpone, Sarah Azimi, Ludovica Bozzoli, Boyang Du, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Cesar Boatella Polo, David Merodio Codinachs
Published in: 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2018, Page(s) 120-126
DOI: 10.1109/AHS.2018.8541474

DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs

Author(s): Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Moritz Fieback, Leticia Bolzani Poehls, Said Hamdioui
Published in: 2019 IEEE European Test Symposium (ETS), 2019, Page(s) 1-2
DOI: 10.1109/ets.2019.8791517

On the evaluation of SEU effects in GPGPUs

Author(s): B. Du, Josie E. Rodriguez Condia, M. Sonza Reorda, L. Sterpone
Published in: 2019 IEEE Latin American Test Symposium (LATS), 2019, Page(s) 1-6
DOI: 10.1109/latw.2019.8704643

An extended GPGPU model to support detailed reliability analysis

Author(s): Josie E. Rodriguez Condia, Matteo Sonza Reorda
Published in: SELSE-15: The 15th Workshop on Silicon Errors in Logic – System Effects, Issue 27-28 March 2019, Stanford, California, USA, 2019

IN-FIELD GPGPU TEST WITH SBST TECHNIQUES

Author(s): B. Du, Josie E. Rodriguez Condia, M. Sonza Reorda, L. Sterpone
Published in: NVIDIA GPU Tecnology Conference (GTC Europe 2018), Issue 23-25 October, 2018, Munich, Germany, 2018

A New Technique to Generate Test Sequences for Reconfigurable Scan Networks

Author(s): Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero
Published in: 2018 IEEE International Test Conference (ITC), 2018, Page(s) 1-9
DOI: 10.1109/test.2018.8624742

Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks

Author(s): A. Damljanovic, A. Jutman, G. Squillero and A. Tsertov
Published in: Proc. IEEE European Test Symposium 2019 (in press), 2019
DOI: 10.5281/zenodo.3362602

Comparing different approaches to the test of Reconfigurable Scan Networks

Author(s): R. Cantoro, A.Damljanovic. M. Sonza Reorda and G. Squillero
Published in: 2018 3rd International Test Standards Application Workshop (TESTA), 2018

Single-Event Characterization of Xilinx UltraScale+ ® MPSOC under Standard and Ultra-High Energy Heavy-Ion Irradiation

Author(s): Maximilien Glorieux, Adrian Evans, Thomas Lange, A-Duong In, Dan Alexandrescu, Cesar Boatella-Polo, Ruben Garcia Alia, Maris Tali, Carlos Urbina Ortega, Maria Kastriotou, Pablo Fernandez-Martinez, Veronique Ferlet-Cavrois
Published in: 2018 IEEE Nuclear & Space Radiation Effects Conference (NSREC 2018), 2018, Page(s) 1-5
DOI: 10.1109/nsrec.2018.8584296

Towards Multidimensional Verification: Where Functional Meets Non-Functional

Author(s): Maksim Jenihhin, Xinhui Lai, Tara Ghasempouri, Jaan Raik
Published in: 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2018, Page(s) 1-7
DOI: 10.1109/norchip.2018.8573495

Mixed-level identification of fault redundancy in microprocessors

Author(s): Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gursoy, Jaan Raik
Published in: 2019 IEEE Latin American Test Symposium (LATS), 2019, Page(s) 1-6
DOI: 10.1109/latw.2019.8704591

Software-Based Mitigation for Memory Address Decoder Aging

Author(s): D.H.P. Kraak, C.C. Gursoy, I.O. Agbo, M. Taouil, M. Jenihhin, J. Raik, S. Hamdioui
Published in: 2019 IEEE Latin American Test Symposium (LATS), 2019, Page(s) 1-6
DOI: 10.1109/latw.2019.8704595

Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits

Author(s): Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
Published in: 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019, Page(s) 7-14
DOI: 10.1109/iolts.2019.8854423

RESCUE EDA Toolset for Interdependent Aspects of Reliability, Security and Quality in Nanoelectronic Systems Design

Author(s): C. C. Gürsoy, G. Medeiros, J. Chen, N. George, J. E. Rodriguez Condia, T. Lange, A. Damljanovic, A. Balakrishnan, R. Segabinazzi Ferreira, X. Lai, S. Masoumian, D. Petryk, T. Koylu, F. da Silva, A. Bagbaba, S. Hamdioui, M. Taouil, M. Krstic, P. Langendörfer, Z. Dyka, M. Huebner, J. Nolte, H. T. Vierhaus,M. Sonza Reorda, G. Squillero, L. Sterpone, J. Raik, D. Alexandrescu, M. Glorieux, G. Selimis
Published in: University Booth - Design, Automation & Test in Europe Conference & Exhibition (Univerity Booth DATE 2019), Issue 25-29 March 2019, 2019
DOI: 10.5281/zenodo.3362529

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors

Author(s): Adeboye Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gursoy, Jaan Raik
Published in: Proc. IEEE European Test Symposium 2019 (in press), 2019

RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality

Author(s): Heinrich Theodor Vierhaus, Maksim Jenihhin, Matteo Sonza Reorda
Published in: 2018 12th European Workshop on Microelectronics Education (EWME), 2018, Page(s) 45-50
DOI: 10.1109/ewme.2018.8629465

A Particle Detector Based on Pulse Stretching Inverter Chain

Author(s): Marko Andjelkovic, Mitko Veleski, Junchao Chen, Aleksandar Simevski, Milos Krstic, Rolf Kraemer
Published in: 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019, Page(s) 594-597
DOI: 10.1109/icecs46596.2019.8964644

Error Rate Calculation of Functional Failures Induced by Single-Event Transients in Clock Distribution Networks

Author(s): T. Lange; M. Glorieux; D. Alexandrescu; L. Sterpone
Published in: 2020

Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL

Author(s): Aleksa Damljanovic, Artur Jutman, Michele Portolan, Ernesto Sanchez, Giovanni Squillero, Anton Tsertov
Published in: 2019 IEEE International Test Conference (ITC), 2019, Page(s) 1-8
DOI: 10.1109/itc44170.2019.9000181

RNN-Based Detection of Fault Attacks on RSA

Author(s): Troya Cagail Koylu, Cezar Rodolfo Wedig Reinbrecht, Said Hamdioui, Mottaqiallah Taouil
Published in: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, Page(s) 1-5
DOI: 10.1109/iscas45731.2020.9180708

Efficient Methodology for ISO26262 Functional Safety Verification

Author(s): Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Said Hamdioui, Christian Sauer
Published in: 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019, Page(s) 255-256
DOI: 10.1109/iolts.2019.8854449

Representing Gate-Level SET Faults by Multiple SEU Faults at RTL

Author(s): Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer
Published in: 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2020, Page(s) 1-6
DOI: 10.1109/iolts50870.2020.9159715

Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks

Author(s): Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Annachiara Ruospo, Riccardo Mariani, Ghani Kanawati, Ernesto Sanchez, Matteo Sonza Reorda, Maksim Jenihhin, Said Hamdioui, Christian Sauer
Published in: 2020 IEEE 38th VLSI Test Symposium (VTS), 2020, Page(s) 1-9
DOI: 10.1109/vts48691.2020.9107599

Evaluation of the Sensitivity of RRAM Cells to Optical Fault Injection Attacks

Author(s): Dmytro Petryk, Zoya Dyka, Eduardo Perez, Mamathamba Kalishettyhalli Mahadevaiaha, Ievgen Kabin, Christian Wenger, Peter Langendorfer
Published in: 2020 23rd Euromicro Conference on Digital System Design (DSD), 2020, Page(s) 238-245
DOI: 10.1109/dsd51259.2020.00047

Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors

Author(s): Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin
Published in: 2019 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2019, Page(s) 72-78
DOI: 10.1109/ahs.2019.00007

PASCAL: Timing SCA Resistant Design and Verification Flow

Author(s): Xinhui Lai, Maksim Jenihhin, Jaan Raik, Kolin Paul
Published in: 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019, Page(s) 239-242
DOI: 10.1109/iolts.2019.8854458

Monitoring of Particle Flux and LET Variations with Pulse Stretching Inverters

Author(s): M. Andjelkovic, J. Chen, A. Simevski, Z. Stamenkovic, M. Krstic, R. Kraemer
Published in: Proc. 31st European Conference on Radiation and its Effects on Components and Systems, 2020

Low latency reconfiguration mechanism for fine-grained processor internal functional units

Author(s): Raphael Segabinazzi Ferreira, Jorg Nolte
Published in: 2019 IEEE Latin American Test Symposium (LATS), 2019, Page(s) 1-6
DOI: 10.1109/latw.2019.8704560

Challenges of Reliability Assessment and Enhancement in Autonomous Systems

Author(s): Maksim Jenihhin, Matteo Sonza Reorda, Aneesh Balakrishnan, Dan Alexandrescu
Published in: 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2019, Page(s) 1-6
DOI: 10.1109/dft.2019.8875379

Sensitivity of Standard Library Cells to Optical Fault Injection Attacks in IHP 250 nm Technology

Author(s): Dmytro Petryk, Zoya Dyka, Peter Langendorfer
Published in: 2020 9th Mediterranean Conference on Embedded Computing (MECO), 2020, Page(s) 1-4
DOI: 10.1109/meco49872.2020.9134146

The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications

Author(s): Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin
Published in: 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2019, Page(s) 1-7
DOI: 10.1109/norchip.2019.8906974

An extended model to support detailed GPGPU reliability analysis

Author(s): B. Du, Josie E. Rodriguez Condia, Matteo Sonza Reorda
Published in: 2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), 2019, Page(s) 1-6
DOI: 10.1109/dtis.2019.8735047

Towards the Use of Machine Learning to Estimate the Functional Failure Rate of Complex Circuits

Author(s): T. Lange; A. Balakrishnan; M. Glorieux; D. Alexandrescu; L. Sterpone
Published in: 2020

RESCUED: A Rescue Demonstrator for Interdependent Aspects of Reliability, Security and Quality Towards a Complete EDA Flow

Author(s): C.C. Gursoy, G. Medeiros, J. Chen, N. George, J.E. Rodriguez Condia, T. Lange, A. Damljanovic, A. Balakrishnan, R. Segabinazzi Ferreira, X. Lai, S. Masoumian, D. Petryk, T. Koylu, F. da Silva, A. Bagbaba, S.Hamdioui, M.Taouil, M.Krstic, P.Langend ̈orfer, Z.Dyka, M.Brandalero, M.H ̈ubner, J.N ̈olte, H.T.Vierhaus, M.Sonza Reorda, G.Squillero, L.Sterpone, J.Raik, D.Alexandrescu, M.Glorieux, G.Seli
Published in: 2020

Soft-Error Rate Due to Single-Event Transients in Clock Distribution Networks

Author(s): Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
Published in: 8th Biannual European - Latin American Summer School on Design, Test and Reliability, Issue 20-22 June 2018, 2018

Application of Graph Neural Network for Estimating Probabilistic Inferences in the Combinational Circuits (workshop poster with abstract)

Author(s): Aneesh Balakrishnan
Published in: Proc. 8th Biannual European - Latin American Summer School on Design, Test and Reliability, Issue 20-22 June 2018, 2018

An Enhanced Evolutionary Technique for the Generation of Compact Reconfigurable Scan-Network Tests

Author(s): Riccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero
Published in: Journal of Circuits, Systems and Computers, Issue 28/supp01, 2019, Page(s) 1940007, ISSN 0218-1266
DOI: 10.1142/s0218126619400073

Understanding multidimensional verification: Where functional meets non-functional

Author(s): Xinhui Lai, Aneesh Balakrishnan, Thomas Lange, Maksim Jenihhin, Tara Ghasempouri, Jaan Raik, Dan Alexandrescu
Published in: Microprocessors and Microsystems, Issue 71, 2019, Page(s) 102867, ISSN 0141-9331
DOI: 10.1016/j.micpro.2019.102867

FlexGripPlus: An improved GPGPU model to support reliability analysis

Author(s): Josie E. RodriguezCondia, Boyang Du, Matteo Sonza Reorda, Luca Sterpone
Published in: Microelectronics Reliability, 2020, ISSN 0026-2714
DOI: 10.1016/j.microrel.2020.113660

"""Improving GPU Register File Reliability with a comprehensive ISA extension"""

Author(s): M. M. Goncalves; Josie E. Rodriguez Condia; M. Sonza Reorda, L. Sterpone and J. R. Azambuja
Published in: Microelectronics Reliability, Issue Volume 114, November 2020 113768, 2020, ISSN 0026-2714
DOI: 10.1016/j.microrel.2020.113768

Prediction of solar particle events with SRAM-based soft error rate monitor and supervised machine learning

Author(s): J. Chen, T. Lange, M. Andjelkovic, A. Simevski, M. Krstic
Published in: Microelectronics Reliability, Issue 114, 2020, Page(s) 113799, ISSN 0026-2714
DOI: 10.1016/j.microrel.2020.113799

DYRE: a DYnamic REconfigurable solution to increase GPGPU’s reliability

Author(s): Josie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone
Published in: The Journal of Supercomputing, 2021, ISSN 0920-8542
DOI: 10.1007/s11227-021-03751-2

An on-line testing technique for the scheduler memory of a GPGPU

Author(s): S. Di Carlo, J. E. Rodriguez Condia and M. Sonza Reorda
Published in: IEEE Access, 2020, ISSN 2169-3536
DOI: 10.1109/access.2020.2968139

A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

Author(s): G.C. Medeiros, L.M. Bolzani Poehls, M. Taouil, F. Luis Vargas, S. Hamdioui
Published in: Microelectronics Reliability, Issue 88-90, 2018, Page(s) 355-359, ISSN 0026-2714
DOI: 10.1016/j.microrel.2018.07.092

Double cell upsets mitigation through triple modular redundancy

Author(s): Yuanqing Li, Anselm Breitenreiter, Marko Andjelkovic, Junchao Chen, Milan Babic, Milos Krstic
Published in: Microelectronics Journal, Issue 96, 2020, Page(s) 104683, ISSN 0026-2692
DOI: 10.1016/j.mejo.2019.104683