Today, wireless communication has changed the way people lived and turn a mobile device into a necessary equipment in daily life. This has driven the cellular phone industry to support Bluetooth wireless personal area networking and 4G communication where low-cost prototype with low power for RF transceivers, as well as processors are integrated in a low-cost and low-power form factor .This project aims to break this tradeoff in conventional PLLs that constraints the amount of noise rejected by the loop as well as the achievable lock time, while maintaining long battery life time at low cost. Instead of detecting only the phase information for a subsequent correction in each reference cycle [see Fig. 2 (c)], waveform information is captured which is composed of amplitude, phase, and frequency information; hence the term wave-locked loop (WLL). The WLL would be able to provide precise frequency with much faster locking when compared to conventional PLLs. To achieve optimum performance, oscillator phase noise is one of the most important design parameters (out-of-band region). Moreover, design of low-flicker-noise LC DCO and small-sized ring oscillator with phase noise filtering will be investigated. Thus, the research objective of this fellowship program is to produce an innovative frequency synthesizer and clock generation systems using wave-locked loop, which includes the study of oversampling of oscillator waveform for fine phase detection, the study of phase-noise reduction in ring oscillator using discrete-time filtering, the study of mm-wave oscillator with flicker noise corner reduction, and system integration for wave-locked loop system.
